Substrate contact opening

Patent metadata

Field	Value
Publication number	US-9275964-B2
Application number	US-201414184849-A
Country	US
Kind code	B2
Filing date	Feb 20, 2014
Priority date	May 20, 2010
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

An under-bump metallization (UBM) structure for a substrate, such as an organic substrate, a ceramic substrate, a silicon or glass interposer, a high density interconnect, a printed circuit board, or the like, is provided. A buffer layer is formed over a contact pad on the substrate such that at least a portion of the contact pad is exposed. A conductor pad is formed within the opening and extends over at least a portion of the buffer layer. The conductor pad may have a uniform thickness and/or a non-planar surface. The substrate may be attached to another substrate and/or a die.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
providing a first substrate having a first electrical contact on a first side and a second electrical contact on a second side;
forming a first buffer layer overlying the first electrical contact, the first buffer layer having a first opening over at least a portion of the first electrical contact;
forming a first conductor pad, the first conductor pad extending over a top surface of the first buffer layer, the first conductor pad having a uniform thickness;
providing a second substrate having a third electrical contact on a third side;
forming a second buffer layer overlying the third electrical contact, the second buffer layer having a second opening over at least a portion of the third electrical contact;
forming a second conductor pad, the second conductor pad extending over a top surface of the second buffer layer, the second conductor pad having a non-planar upper surface; and
attaching the first substrate to the second substrate using a conductive element, the conductive element being in direct contact with the first conductor pad and the second conductor pad.

2. The method of claim 1 , wherein the first buffer layer comprises a polymer, an epoxy, a polyimide, a solder resist, or a photo-sensitive material.

3. The method of claim 1 , wherein the first buffer layer comprises a bump buffer layer, and the first conductor pad comprises a first bump conductor pad.

4. The method of claim 1 , wherein the first buffer layer comprises a ball buffer layer, and the first conductor pad comprises a ball conductor pad.

5. The method of claim 1 , further comprising:
forming a third buffer layer over the first conductor pad, the third buffer layer having a third opening over at least a portion of the first conductor pad; and
forming a third conductor pad, the third conductor pad extending over a top surface of the third buffer layer and having a uniform thickness.

6. The method of claim 1 , wherein the first substrate comprises an organic substrate, a high density interconnect, a printed circuit board, or a silicon interposer.

7. The method of claim 1 , wherein a thickness of the first conductor pad is less than about 10 μm.

8. The method of claim 1 , wherein the first conductor pad comprises a composite layer.

9. A method of forming a semiconductor device, the method comprising:
providing a first substrate having a first contact pad on a first side;
forming one or more buffer layers overlying the first contact pad, wherein a first buffer layer of the one or more buffer layers has an opening, at least a portion of the first contact pad being exposed in the opening;
forming one or more conductor pads on the first side of the first substrate, wherein a first conductor pad of the one or more conductor pads extends over sidewalls of the opening in the first buffer layer, the first conductor pad having a non-planar upper surface and extending over at least a portion of the first buffer layer;
providing an integrated circuit having a second substrate, the second substrate having a second contact pad on a second side;
forming a passivation layer overlying the second contact pad;
forming a second conductor pad on the second side of the second substrate, a first portion of the second conductor pad extending through the passivation layer and contacting the second contact pad, a second portion of the second conductor pad extending over a top surface of the passivation layer; and
forming a conductive element interposed between the first substrate and the second substrate, the conductive element being in direct contact with an uppermost conductor pad of the first substrate and the second conductor pad of the second substrate;
wherein each of any remaining buffer layers has an opening exposing at least a portion of an underlying conductor pad; and
wherein each of any remaining conductor pads extends over sidewalls of a corresponding one of the buffer layers, each of the remaining conductor pads having a non-planar upper surface and extending over at least a portion of the corresponding one of the buffer layers.

10. The method of claim 9 , wherein the conductive element is a conductive bump element.

11. The method of claim 10 , wherein the conductive bump element is a solder bump.

12. The method of claim 9 , wherein the one or more conductor pads have a uniform thickness.

13. The method of claim 9 , wherein the semiconductor device comprises two buffer layers.

14. The method of claim 9 , wherein the one or more buffer layers are one or more bump buffer layers and the one or more conductor pads are one or more bump conductor pads, and further comprising:
forming a ball buffer layer on a third side of the first substrate, the third side of the first substrate being opposite the first side of the first substrate, the ball buffer layer having an opening over at least a portion of an electrical contact; and
forming a ball conductor pad, the ball conductor pad having a uniform thickness and extending over a top surface of the ball buffer layer, the ball conductor pad contacting the electrical contact.

15. The method of claim 14 , further comprising:
providing a third substrate having another buffer layer, wherein the another buffer layer has another conductor pad, the another conductor pad extending through the another buffer layer and having a uniform thickness; and
forming another conductive element interposed between the first substrate and the third substrate, the another conductive element being in direct contact with the ball conductor pad of the first substrate.

16. A method of forming a semiconductor device, the method comprising:
providing a first substrate having a first electrical contact on a first side and a second electrical contact on a second side;
forming a first bump buffer layer overlying the first electrical contact, the first bump buffer layer having a first opening over at least a portion of the first electrical contact;
forming a first bump conductor pad, the first bump conductor pad extending over a top surface of the first bump buffer layer, the first bump conductor pad having a uniform thickness;
forming a first ball buffer layer overlying the second electrical contact, the first ball buffer layer having a second opening over at least a portion of the second electrical contact;
forming a first ball conductor pad, the first ball conductor pad extending over a top surface of the first ball buffer layer, the first ball conductor pad having a uniform thickness;
forming a solder bump, the solder bump being in direct contact with the first bump conductor pad;
forming a solder ball, the solder ball being in direct contact with the first ball conductor pad;
attaching a second substrate to the first side of the first substrate, an external contact pad of the second substrate being in direct contact with the solder bump; and
attaching a third substrate to the second side of the first substrate, an external contact pad of the third substrate being in direct contact with the solder ball.

17. The method of claim 16 , wherein the first ball conductor pad has a non-planar upper surface.

18. The method of claim 16 , wherein the first bump conductor pad has a non-planar upper surface.

19. The method of claim 16 , further comprising:
forming a second bump buffer layer under the first bump buffer layer, the second bump buffer layer having an opening over at least a portion of the first electrical contact; and
forming a second bum

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Yu Chen-Hua
• Wu Jiun Yi

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/147

  the encapsulations being multilayered · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title