Reduced volume interconnect for three-dimensional chip stack

Patent metadata

Field	Value
Publication number	US-2016240501-A1
Application number	US-201615135599-A
Country	US
Kind code	A1
Filing date	Apr 22, 2016
Priority date	Jan 19, 2015
Publication date	Aug 18, 2016
Grant date	—

Abstract

A method of forming a reduced volume interconnect for a chip stack including multiple silicon layers, the method including: forming multiple conductive structures, each of at least a subset of the conductive structures having a volume of conductive material for a corresponding under bump metallurgy pad onto which the conductive structure is transferred that is configured such that a ratio of an unreflowed diameter of the conductive structure to a diameter of the corresponding pad is about one third-to-one or less; transferring the conductive structures to the silicon layers; stacking the silicon layers in a substantially vertical dimension such that each of the conductive structures on a given silicon layer is aligned with a corresponding electrical contact location on an underside of an adjacent silicon layer; and heating the interconnect so as to metallurgically bond multiple electrical contact locations of adjacent silicon layers.

First claim

What is claimed is:

1 . A reduced volume electrical interconnect for a chip stack, the interconnect comprising:
a plurality of silicon layers having multiple electrical contact locations formed on a surface thereof; a plurality of under bump metallurgy (UBM) pads, each of the UBM pads being formed between a corresponding one of the silicon layers and a corresponding one of the electrical contact locations; and a plurality of conductive structures, each of the conductive structures being aligned with a corresponding one of the electrical contact locations and having a volume of conductive material for a corresponding one of the UBM pads that is configured such that a ratio of an unreflowed diameter of the conductive structure to a diameter of the corresponding pad is about one third-to-one or less; wherein the plurality of silicon layers are stacked in a substantially vertical dimension such that each of the conductive structures on a given silicon layer is aligned with a corresponding electrical contact location on an underside of an adjacent silicon layer, the conductive structures, when heated to a prescribed temperature, metallurgically bonding the electrical contact locations of adjacent silicon layers in such a manner that at least a given one of the conductive structures between aligned electrical contact locations on corresponding adjacent silicon layers collapses to thereby reduce an interconnect gap therebetween.

2 . The electrical interconnect of claim 1 , wherein each of the UBM pads is formed of a material which, when bonded with a corresponding one of the plurality of conductive structures, forms intermetallic compounds in a junction between the conductive structure and a corresponding UBM pad, the intermetallic compounds in the conductive structures increasing a melting temperature of the conductive structures which reduces reflow of the conductive structures when the electrical interconnect is subjected to subsequent processing.

3 . The electrical interconnect of claim 1 , wherein at least two of the plurality of conductive structures are transferred to a single corresponding UBM pad, an aggregate volume of conductive material forming the at least two conductive structures being substantially equal to a volume of a single conductive structure having a ratio of an unreflowed diameter of the single conductive structure to the diameter of the corresponding pad of about one third-to-one or less.

4 . The electrical interconnect of claim 1 , wherein the volume of conductive material forming each of at least a subset of the conductive structures is configured such that a percentage of intermetallic compounds in a junction between the conductive structure and corresponding aligned UBM pads is about forty percent or more of a total volume of conductive material.

5 . A reduced volume electrical interconnect for a chip stack, the interconnect comprising:
a plurality of silicon layers having multiple electrical contact locations formed on a surface thereof; a plurality of under bump metallurgy (UBM) pads, each of the UBM pads being formed between a corresponding one of the silicon layers and a corresponding one of the electrical contact locations; and a plurality of conductive structures, each of the conductive structures being aligned with a corresponding one of the electrical contact locations and having a volume of conductive material for a corresponding one of the UBM pads that is configured such that a ratio of an unreflowed diameter of the conductive structure to a diameter of the corresponding pad is about one third-to-one or less; wherein each of at least a subset of the conductive structures is formed having a volume of conductive material that is configured such that a percentage of intermetallic compounds in a junction between the conductive structure and corresponding aligned UBM pads formed on corresponding opposing surfaces of adjacent silicon layers is about forty percent or more of a total volume of conductive material.

Assignees

• IBM

Inventors

• Gruber Peter A
• Sakuma Katsuyuki
• Shih Da-Yuan

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title