Chip packaging structures

Patent metadata

Field	Value
Publication number	US-2016336285-A1
Application number	US-201615221856-A
Country	US
Kind code	A1
Filing date	Jul 28, 2016
Priority date	May 12, 2014
Publication date	Nov 17, 2016
Grant date	—

Abstract

A method for treating a chip packaging structure includes providing a chip packaging structure having at least a first electrical connect structure and a second electrical connect structure, and an insulation layer exposing portions of the first electrical connect structure and the second electrical connect structure; selecting a plasma gas based on materials of the first electrical connect structure and the second electrical connect structure and a type of process forming the first electrical connect structure and the second electrical connect structure, wherein metal cations are left on the insulation layer; performing a plasma treatment process using the selected plasma gas on the first electrical connect structure, the second electrical connect structure and the insulation layer, causing reaction of the metal cations to substantially convert the metal cations into electrically neutral materials; and removing the reacted metal cations from the insulation layer.

First claim

1 .- 13 . (canceled)

14 . A chip packaging structure, comprising:
a substrate having a plurality of devices; a metal interconnect structure electrically connecting with the devices formed on the substrate; at least a first electrical connect structure and a second electrical connect structure electrically connecting with the metal interconnect structure formed over the metal interconnect structure; and an insulation layer insulating the first electrical connect structure and the second electrical connect structure and also exposing portion or all of the first electrical connect structure and the second electrical connect structure, wherein the insulation has a material structure being treated by a plasma treatment process using a plasma gas, selected based on materials of the first electrical connect structure and the second electrical connect structure and a type of process forming the first electrical connect structure and the second electrical connect structure, including one of at least oxygen and nitrogen to remove metal cations on its surface formed over the metal interconnect to electrical insulate the first electrical connect structure and the second electrical connect structure.

15 . The chip packaging structure according to claim 14 , wherein:
the first electrical connect structure is a first soldering pad; and the second electrical connect structure is a second soldering pad.

16 . The chip packaging structure according to claim 14 , wherein:
the first electrical connect structure is a first re-distribution layer; and the second electrical connect structure is a second re-distribution layer.

17 . The chip packaging structure according to claim 15 , wherein:
the first electrical connect structure includes a first soldering ball formed on the first soldering pad; and the second electrical connect structure includes a second soldering ball formed on the second soldering pad.

18 . The chip packaging structure according to claim 16 , wherein:
the first electrical connect structure includes a first soldering ball formed on the first re-distribution layer; and the second electrical connect structure includes a second soldering ball formed on the second re-distribution layer

19 . The chip packaging structure according to claim 17 , wherein:
the first soldering pad and the second soldering pad are made of one of Cu and Al; and the first soldering ball and the second soldering ball are made of one of Cu, Sn and Ag.

20 . The chip packaging structure according to claim 17 , wherein:
a first under-ball metal layer is formed between the first soldering pad and the first soldering ball; and a second under-ball metal layer is formed between the second soldering pad and the second soldering ball.

21 . The chip packaging structure according to claim 16 , wherein:
the first re-distribution layer and the second re-distribution layer are made of one of Cu and Al.

22 . The chip packaging structure according to claim 18 , wherein:
a first under-ball metal layer is formed between the first soldering ball and the first re-distributing layer; and a second under-ball metal layer is formed between the second soldering ball and the second re-distributing layer.

23 . The chip packaging structure according to claim 19 , wherein:
the first under-ball metal layer and the second under-ball metal layer are made of one of Ti and Cu.

24 . The chip packaging structure according to claim 14 , wherein:
the insulation layer is made of one of silicon oxide, silicon nitride and polyimide.

Assignees

• Semiconductor Mfg Int Shanghai Corp

Inventors

• Wang Qifeng

Classifications

• H10P70/27

  during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/07211

  Treating the bond pad before connecting, e.g. by applying flux or cleaning · CPC title

• H10W72/01971

  Cleaning, e.g. oxide removal · CPC title

• H10W72/01953

  by etching · CPC title