Semiconductor device having solderable and bondable electrical contact pads

Patent metadata

Field	Value
Publication number	US-9496237-B2
Application number	US-201514715778-A
Country	US
Kind code	B2
Filing date	May 19, 2015
Priority date	May 19, 2014
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

A semiconductor device includes a semiconductor chip and a plurality of electrical contact pads disposed on a main face of the semiconductor chip, wherein the electrical contact pads each include a layer stack, each layer stack having one and the same order of layers, and wherein the electrical contact pads are both solderable and bondable.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a semiconductor chip; and
a plurality of electrical contact pads disposed on a main face of the semiconductor chip, wherein
the electrical contact pads comprise a top layer stack, each top layer stack in the plurality comprising a plurality of layers arranged in the same order, and wherein
the electrical contact pads are both solderable and wire bondable,
wherein a first group of the electrical contact pads has first lateral dimensions and a second group of electrical contact pads has second lateral dimensions,
wherein the first lateral dimensions are smaller than the second lateral dimensions,
wherein the first group of the electrical contact pads is disposed at a center of the semiconductor chip, and
wherein the second group of the electrical contact pads forms a ring disposed at a periphery of the semiconductor chip that encloses the first group of the electrical contact pads.

2. The semiconductor device according to claim 1 , wherein
each layer stack comprises a first lower Ni-based layer; and
a second upper Au-based layer;
wherein an upper surface of the second layer is connectable to a further semiconductor device or a bond wire.

3. The semiconductor device according to claim 2 , wherein
each layer stack further comprises a third Pd-based layer disposed between the first and second layers.

4. The semiconductor device according to claim 2 , wherein
the first lower Ni-based layer contains P.

5. The semiconductor device according to claim 4 , wherein
the amount of P is in a range from greater than 4% to less than or equal to 12%.

6. The semiconductor device according to claim 1 , further comprising:
a dam disposed on the main face between the first and second groups of the electrical contact pads and being formed in a ring that surrounds the first group of the electrical contact pads.

7. The semiconductor device according to claim 6 , wherein
the dam is formed either of one or more of the materials of the layer stacks or of a polymer material.

8. The semiconductor device according to claim 6 , wherein the dam is formed of one or more of the materials of the layer stacks.

9. The semiconductor device according to claim 6 , wherein the dam is disposed on an exposed portion of the main face of the semiconductor chip that extends between the first and second groups of the electrical contact pads, and wherein the dam provides a vertical protrusion extending away from the exposed portion of the main face of the semiconductor chip so as to prevent liquefied material from flowing between the first and second groups of the electrical contact pads.

10. A semiconductor device, comprising:
a semiconductor chip; and
a plurality of electrical contact pads disposed on a main face of the semiconductor chip, wherein
the electrical contact pads or one or more groups of the electrical contact pads comprise a layer stack, each layer stack comprising
a first lower Ni-based layer, and
a second upper Au-based layer,
wherein an upper surface of the second layer is connectable to a further semiconductor device or a bond wire,
wherein a first group of the electrical contact pads has first lateral dimensions and a second group of electrical contact pads has second lateral dimensions,
wherein the first lateral dimensions are smaller than the second lateral dimensions,
wherein the first group of the electrical contact pads is disposed at a center of the semiconductor chip, and
wherein the second group of the of the electrical contact pads forms a ring disposed at a periphery of the semiconductor chip that encloses the first group of the electrical contact pads.

11. The semiconductor device according to claim 10 , further comprising:
a third Pd-based layer disposed between the first and second layers.

12. The semiconductor device according to claim 10 , wherein
the first lower Ni-based layer contains P.

13. The semiconductor device according to claim 12 , wherein
the amount of P is in a range from greater than 0% to less or equal than 12%.

14. The semiconductor device according to claim 10 , further comprising:
a dam disposed on the main face between the first and second groups of the electrical contact pads and being formed in a ring that surrounds the first group of the electrical contact pads.

15. The semiconductor device according to claim 14 , wherein the dam is disposed on an exposed portion of the main face of the semiconductor chip that extends between the first and second groups of the electrical contact pads, and wherein the dam provides a vertical protrusion extending away from the exposed portion of the main face of the semiconductor chip so as to prevent liquefied material from flowing between the first and second groups of the electrical contact pads.

16. The semiconductor device according to claim 10 , further comprising:
a further semiconductor chip comprising electrical contact elements and being disposed above the semiconductor chip, wherein the electrical contact elements are connected with a group of the plurality of electrical contact pads.

17. A method for fabricating a semiconductor device, comprising:
providing a semiconductor die;
fabricating a plurality of electrical contact pads on a main face of the semiconductor die, wherein
the electrical contact pads comprise a layer stack, each layer stack comprising a plurality of layers arranged in the same order; and wherein
the electrical contact pads are both solderable and wire bondable,
wherein a first group of the electrical contact pads has first lateral dimensions and a second group of electrical contact pads has second lateral dimensions,
wherein the first lateral dimensions are smaller than the second lateral dimensions,
wherein the first group of the electrical contact pads is disposed at a center of the semiconductor die, and
wherein the second group of the of the electrical contact pads forms a ring disposed at a periphery of the semiconductor die that encloses the first group of the electrical contact pads.

18. The method according to claim 17 , wherein
fabricating the plurality of electrical contact pads comprises either one of galvanical plating or electroless plating.

19. The method according to claim 17 , wherein
fabricating the plurality of electrical contact pads comprises depositing a first Ni-based layer onto electrical contact elements on the main face of the semiconductor chip; and
depositing a second Au-based layer above the first Ni-based layer such that an upper surface of the second layer is connectable to a further semiconductor device or a bond wire.

20. The method according to claim 19 , wherein
fabricating the plurality of electrical contact pads further comprises depositing a Pd based layer between the Ni- and Au-based layer.

Assignees

• Infineon Technologies Ag

Inventors

• Beer Gottfried
• Foerg Raimund
• Hoegerl Juergen

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title