Stress generation in stacked nanosheet architectures
US-2026101542-A1 · Apr 9, 2026 · US
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Wang Junli patents
Wang Junli is listed as an inventor on 907 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Wang Junli |
| Total patents | 907 |
| First publication | Feb 17, 2015 |
| Latest publication | Apr 9, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Discontinuous high dielectric constant (hk) layer
US-2026096147-A1 · Apr 2, 2026 · US
Stacked fet with flexible inter-epi dielectric thickness
US-2026096199-A1 · Apr 2, 2026 · US
Shallow and deep contacts with stitching
US-12593668-B2 · Mar 31, 2026 · US
Self-aligned backside contact with increased contact area
US-12593468-B2 · Mar 31, 2026 · US
Common self aligned gate contact for stacked transistor structures
US-12581702-B2 · Mar 17, 2026 · US
High density memory with stacked nanosheet transistors
US-12575113-B2 · Mar 10, 2026 · US
Placeholder profile formation for backside contact
US-12568669-B2 · Mar 3, 2026 · US
Stacked random-access-memory with complementary adjacent cells
US-12563715-B2 · Feb 24, 2026 · US
Method and structure for a logic device and another device
US-12557353-B2 · Feb 17, 2026 · US
Recent patents
Latest publications not already listed above.
Static random access memory device with stacked fets
US-2024431087-A1 · Dec 26, 2024 · US
Two-dimensional (2d) self-aligned contact (or via) to enable further device scaling
US-2020411376-A1 · Dec 31, 2020 · US
Self-aligned tunneling field effect transistors
US-10833180-B2 · Nov 10, 2020 · US
Capacitors
US-10833149-B2 · Nov 10, 2020 · US
Multiple width nanosheet devices
US-10833204-B2 · Nov 10, 2020 · US
Fin cut forming single and double diffusion breaks
US-2020343144-A1 · Oct 29, 2020 · US
Finfet devices
US-2020328124-A1 · Oct 15, 2020 · US
Self-aligned top spacers for vertical FETs with in situ solid state doping
US-10777469-B2 · Sep 15, 2020 · US
Vertical fin field effect transistor devices with a replacement metal gate
US-10679993-B2 · Jun 9, 2020 · US
Vertical FET with shaped spacer to reduce parasitic capacitance
US-10672887-B2 · Jun 2, 2020 · US
Vertical transistor and method of forming the vertical transistor
US-2020167331-A1 · May 28, 2020 · US
Gate Contact Over Active Enabled by Alternative Spacer Scheme and Claw-Shaped Cap
US-2020135886-A1 · Apr 30, 2020 · US
Integration of input/output device in vertical field-effect transistor technology
US-10615276-B2 · Apr 7, 2020 · US
Vertical fet with shaped spacer to reduce parasitic capacitance
US-2020083347-A1 · Mar 12, 2020 · US
Replacement metal gate structures
US-10573726-B2 · Feb 25, 2020 · US
Vertical transistor device
US-10573727-B2 · Feb 25, 2020 · US
Shared contact trench comprising dual silicide layers and dual epitaxial layers for source/drain layers of nfet and pfet devices
US-2020058562-A1 · Feb 20, 2020 · US
Formation of a bottom source-drain for vertical field-effect transistors
US-10553716-B2 · Feb 4, 2020 · US
Replacement metal gate structures
US-2020027967-A1 · Jan 23, 2020 · US
Integration of input/output device in vertical field-effect transistor technology
US-2020013891-A1 · Jan 9, 2020 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 893 |
| Globalfoundries Inc | 33 |
| St Microelectronics Inc | 22 |
| Tessera Inc | 4 |
| Globalfoundries Inc | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D84/038 | 508 |
| H10D64/017 | 369 |
| H10D30/62 | 293 |
| H01L29/66545 | 254 |
| H10D30/024 | 238 |