Integration of input/output device in vertical field-effect transistor technology

Patent metadata

Field	Value
Publication number	US-10615276-B2
Application number	US-201715853071-A
Country	US
Kind code	B2
Filing date	Dec 22, 2017
Priority date	Dec 22, 2017
Publication date	Apr 7, 2020
Grant date	Apr 7, 2020

Abstract

A vertical field-effect transistor (FET) device and an input/output (IO) FET device are formed. The vertical FET device is formed in a vertical FET device area of a substrate and the IO FET device is formed in an IO FET device area of the substrate. Forming the vertical FET device and the IO FET device includes forming a plurality of first fin structures in the vertical FET device area and forming at least two second fin structures in the IO FET device area. The at least two second fin structures are separated by a distance associated with a length of a channel connecting the at least two fin structures in the IO FET device area. The length of the channel is determined based on at least one voltage for implementing the IO FET device.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, comprising:
forming a vertical field-effect transistor (FET) device and an input/output (IO) FET device, wherein the vertical FET device is formed in a vertical FET device area of a substrate and the IO FET device is formed in an IO FET device area of the substrate, and wherein forming the vertical FET device and the IO FET device further comprises:
forming a plurality of first fin structures in the vertical FET device area;
forming at least two second fin structures in the IO FET device area, wherein the at least two second fin structures are separated by a distance associated with a length of a channel connecting the at least two second fin structures, and wherein the length of the channel is determined based on at least one voltage for implementing the IO FET device; and
selectively exposing a portion of the IO FET device area for further processing of the vertical FET and IO FET devices, including selectively removing a portion of a first spacer formed on the substrate in the IO FET device area.

2. The method of claim 1 , further comprising forming a doped region within the IO FET device area prior to forming the plurality of first and second fin structures.

3. The method of claim 1 , wherein forming the vertical FET device and the IO FET device further comprises forming a plurality of shallow trench isolation regions in the substrate prior to forming the first and second fin structures.

4. The method of claim 1 , wherein forming the vertical FET device and the IO FET device further comprises forming the first spacer on the substrate and a first epitaxial layer in the vertical FET device area.

5. The method of claim 1 , wherein selectively removing the portion of the first spacer includes forming a mask over the vertical FET device area and select portions of the IO FET device area, and etching away the spacer from portions of the IO FET device area that are not protected by the mask.

6. The method of claim 1 , wherein forming the vertical FET device and the IO FET device further comprises depositing gate material on the fin structures and the exposed portion of the IO FET device area.

7. The method of claim 1 , wherein each of the first and second fin structures comprises a fin, and wherein the gate material is deposited on the fins.

8. The method of claim 1 , wherein forming the vertical FET device and the IO FET device further comprises forming an interlayer dielectric (ILD) after depositing the gate material.

9. The method of claim 8 , wherein each of the first and second fin structures comprises a cap formed on a fin, and wherein forming the ILD comprises depositing dielectric material on the substrate, planarizing material including the dielectric material down to exposed surfaces of the caps, and performing a selective etch process to remove a portion of the dielectric material to a height below the fins.

10. The method of claim 8 , wherein forming the vertical FET device and the IO FET device further comprises forming a second spacer on the ILD, and forming respective epitaxial layers above the first and second fin structures.

11. The method of claim 10 , wherein forming the vertical FET device and the IO FET device further comprises forming an ILD cap layer, and forming a plurality of first contacts in the vertical FET device area and a plurality of second contacts in the IO FET device area.

12. A method for fabricating a semiconductor device, comprising:
forming a vertical field-effect transistor (FET) device and an input/output (IO) FET device, wherein the vertical FET device is formed in a vertical FET device area of a substrate and the IO FET device is formed in an IO FET device area of the substrate, and wherein forming the vertical FET device and the IO FET device further comprises:
forming a plurality of first fin structures in the vertical FET device area, and at least two second fin structures in the IO FET device area, the at least two second fin structures being separated by a distance associated with a length of a channel connecting the at least two second fin structures, wherein the length of the channel is determined based on at least one voltage for implementing the IO FET device;
forming a first spacer on the substrate;
selectively removing a portion of the first spacer in the IO FET device area to create an exposed portion of the IO FET device area;
depositing gate material on the fin structures and the exposed portion of the IO FET device area;
forming an interlayer dielectric (ILD);
forming a second spacer on the ILD;
forming respective epitaxial layers above the first and second fin structures;
forming an ILD cap layer; and
forming a plurality of first contacts in the vertical FET device area and a plurality of second contacts in the IO FET device area.

13. The method of claim 12 , further comprising:
forming a doped region within the IO FET device area prior to forming the plurality of first and second fin structures;
forming a plurality of shallow trench isolation regions in the substrate; and
forming a first epitaxial layer in the vertical FET device area after forming the first and second fin structures.

14. The method of claim 12 , wherein each of the first and second fin structures comprises a fin, and wherein depositing the gate material on the fin structures comprises depositing the gate material on the fins.

15. The method of claim 12 , wherein each of the first and second fin structures comprises a fin and a cap formed on the fin, wherein the ILD is formed to a height below the fins, and wherein forming the ILD comprises depositing dielectric material on the substrate, planarizing material including the dielectric material down to exposed surfaces of the caps, and performing a selective etch process to remove a portion of the dielectric material to the height below the fins.

Assignees

• IBM

Inventors

• Liu Xuefeng
• Wang Junli
• Anderson Brent A
• Hook Terence B
• Karve Gauri

Classifications

• H01L29/7827 Primary

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic

• H01L21/762

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic

• H01L21/76224

  Electricity · mapped topic