Method and structure for a logic device and another device

Patent metadata

Field	Value
Publication number	US-12557353-B2
Application number	US-202217663676-A
Country	US
Kind code	B2
Filing date	May 17, 2022
Priority date	May 17, 2022
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

A method including forming an oxide layer on a first substrate and forming a second substrate on the oxide layer. Doping a first section of the second substrate while not doping a second section of the second substrate. Forming a first nano device on the second section of the second substrate and forming a second nano device on first section of the second substrate. Flipping the first substrate over to allow for backside processing of the substrate and forming at least one backside contact connected to the first nano device while backside contacts are not formed or connected to the second nano device.

First claim

What is claimed is:

1 . A microelectronic structure comprising:
a first device located on a dielectric layer and a shallow trench isolation layer, wherein the first device is in direct contact with the dielectric layer, wherein the shallow trench isolation layer includes a liner and fill layer, wherein the dielectric layer 1 s located adjacent to and in direct contact with two or more surfaces of the shallow trench isolation layer; a second device located on a semiconductor substrate layer and the shallow trench isolation layer, wherein the second device is in direct contact with the semiconductor substrate layer, wherein the semiconductor substrate layer 1 s located adjacent to and in direct contact with a vertical side surfaces and a horizontal surface of the shallow trench isolation layer, wherein the dielectric layer and the semiconductor substrate layer are located on substantially the same level such that the dielectric layer and the semiconductor substrate layer are located on the same horizontal plane, and a backside contact located in the dielectric layer, wherein the backside contact is connected to the first device and not contacted to the second device.

2 . The microelectronic structure of claim 1 , wherein the first device and the second device are different devices.

3 . The microelectronic structure of claim 1 , wherein the first device is a logic device.

4 . The microelectronic structure of claim 3 , wherein the second device is a diode.

5 . The microelectronic structure of claim 3 , wherein the second device is a bipolar junction transistor.

6 . A microelectronic structure comprising:
a first nano device located on a dielectric layer, wherein the dielectric layer is in contact with the backside of the first nano device; a backside contact located in the dielectric layer, wherein the backside contact is connected to the first nano device; and a second nano device located on a semiconductor substrate, wherein the semiconductor substrate is in direct contact with the backside of the second nano device, wherein the dielectric layer of the first nano device and the semiconductor substrate of the second nano device are located on substantially the same level such that the dielectric layer and the semiconductor substrate are located on the same horizontal plane, wherein the backside contact is not connected to the second nano device.

7 . The microelectronic structure of claim 6 , further comprising:
a backside power network connected to the first nano device through the backside contacts, wherein the backside power network is not connected to the second nano device.

8 . The microelectronic structure of claim 7 , further comprising:
a plurality of frontside contacts, wherein the frontside contacts are connected to the first nano device and the second nano device.

9 . The microelectronic structure of claim 6 , wherein the first nano device is logic device.

10 . The microelectronic structure of claim 8 , wherein the second nano device is a diode.

11 . The microelectronic structure of claim 8 , wherein the second nano device is a bipolar junction transistor.

Assignees

• IBM

Inventors

• Xie Ruilong
• Chou Anthony I
• Anderson Brent A
• Arnold John Christopher
• Wang Junli
• Zhao Kai
• Hook Terence
• Frougier Julien
• Liu Xuefeng

Classifications

• H10P14/3452

  Microstructure · CPC title

• H10P14/2901

  Materials · CPC title

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title

• H10W20/021

  of interconnections within wafers or substrates · CPC title