Multiple width nanosheet devices

Patent metadata

Field	Value
Publication number	US-10833204-B2
Application number	US-201916591873-A
Country	US
Kind code	B2
Filing date	Oct 3, 2019
Priority date	Aug 14, 2018
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

A technique relates to a semiconductor device. A first stack includes a first plurality of nanowires respectively coupled to first source and drain regions, and a second stack includes a second plurality of nanowires respectively coupled to second source and drain regions. First source and drain contacts couple to a first predefined number of the first plurality of nanowires. Second source and drain contacts to couple to a second predefined number of the second plurality of nanowires, wherein the first predefined number is different from the second predefined number.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
forming a first stack comprising first nanowires coupled to first source and drain regions, and a second stack comprising second nanowires coupled to second source and drain regions; and
forming first contacts with a first depth for coupling to a number of exposed sidewalls of the first source and drain regions and second contacts with a second depth for coupling to another number of exposed sidewalls of the second source and drain regions, the number of exposed sidewalls being different from the another number of exposed sidewalls, the first depth being different from the second depth.

2. The method of claim 1 , wherein the first depth corresponds to coupling to a first number of the first nanowires and the second depth corresponds to coupling to a second number of the second nanowires.

3. The method of claim 2 , wherein the first number is different from the second number.

4. The method of claim 1 further comprising forming a third stack comprising third nanowires coupled to third source and drain regions.

5. The method of claim 4 further comprising forming third contacts with a third depth for coupling to the third nanowires.

6. The method of claim 5 , wherein the third depth is different from the first depth and the second depth.

7. A method of forming a semiconductor device, the method comprising:
forming a first stack comprising first nanowires coupled to first source and drain regions, and a second stack comprising second nanowires coupled to second source and drain regions; and
forming first contacts with a first depth for coupling to the first nanowires and second contacts with a second depth for coupling to the second nanowires, the first depth being different from the second depth, wherein the first source and drain regions are directly connected to the first contacts.

8. The method of claim 1 , wherein the second source and drain regions are directly connected to the second contacts.

9. The method of claim 1 , wherein the first source and drain regions are grown from sidewalls of the first nanowires.

10. The method of claim 1 , wherein the second source and drain regions are grown from sidewalls of the second nanowires.

11. A semiconductor device comprising:
a first stack comprising first nanowires coupled to first source and drain regions, and a second stack comprising second nanowires coupled to second source and drain regions; and
first contacts with a first depth for coupling to the first nanowires and second contacts with a second depth for coupling to the second nanowires, the first depth being different from the second depth, wherein the first source and drain regions are directly connected to the first contacts.

12. The semiconductor device of claim 11 , wherein the first depth corresponds to coupling to a first number of the first nanowires and the second depth corresponds to coupling to a second number of the second nanowires.

13. The semiconductor device of claim 12 , wherein the first number is different from the second number.

14. The semiconductor device of claim 11 further comprising a third stack comprising third nanowires coupled to third source and drain regions.

15. The semiconductor device of claim 14 further comprising third contacts with a third depth for coupling to the third nanowires.

16. The semiconductor device of claim 15 , wherein the third depth is different from the first depth and the second depth.

17. The semiconductor device of claim 11 , wherein the second source and drain regions are directly connected to the second contacts.

18. The semiconductor device of claim 11 , wherein the first source and drain regions are grown from sidewalls of the first nanowires.

19. The semiconductor device of claim 11 , wherein the second source and drain regions are grown from sidewalls of the second nanowires.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Clevenger Lawrence A
• Radens Carl
• Wang Junli
• Zhang John H

Classifications

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D64/01

  Manufacture or treatment · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D30/6735 Primary

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/6729

  characterised by the electrodes · CPC title