Vertical FET with shaped spacer to reduce parasitic capacitance

Patent metadata

Field	Value
Publication number	US-10672887-B2
Application number	US-201715838890-A
Country	US
Kind code	B2
Filing date	Dec 12, 2017
Priority date	Dec 12, 2017
Publication date	Jun 2, 2020
Grant date	Jun 2, 2020

Abstract

A vertical transistor includes a first source/drain region and a second source/drain region vertically disposed relative to the first source/drain region and coupled to the first source/drain region by a fin. A gate dielectric is formed on the fin, and a gate conductor is formed on the gate dielectric in a region of the fin. A shaped spacer is configured to cover a lower portion and sides of the second source/drain region to reduce parasitic capacitance between the gate conductor and the second source/drain region.

First claim

What is claimed is:

1. A vertical transistor, comprising:
a first source/drain region;
a second source/drain region vertically disposed relative to the first source/drain region and coupled to the first source/drain region by a fin;
a shaped spacer including a funnel-like interior shape and configured to cover a lower portion and sides of the second source/drain region to reduce parasitic capacitance between a gate conductor and the second source/drain region;
a gate dielectric formed on the fin and conformally extending along a lower portion and a side portion of the shaped spacer.

2. The vertical transistor as recited in claim 1 , wherein the shaped spacer includes an annular configuration wherein the fin is disposed centrally within at least a portion of the shaped spacer.

3. The vertical transistor as recited in claim 2 , wherein the shaped spacer contacts the fin at the lower portion of the shaped spacer.

4. The vertical transistor as recited in claim 1 , wherein the second source/drain region includes a funnel-like shape corresponding to the interior shape of the shaped spacer.

5. The vertical transistor as recited in claim 1 , wherein the gate dielectric is disposed between the shaped spacer and the gate conductor.

6. The vertical transistor as recited in claim 1 , wherein a wall of the shaped spacer includes an L-shaped profile.

7. A method for forming a vertical transistor, comprising:
depositing a dielectric layer around a fin and a dielectric cap on the fin;
removing the cap to form an opening in the dielectric layer over the fin;
etching the dielectric layer in the opening to form contoured side walls;
forming a spacer form in the opening;
recessing the dielectric layer to below the spacer form and to expose a portion of the fin;
forming a shaped spacer about the spacer form;
replacing the spacer form with a source/drain region grown on the fin;
replacing the dielectric layer with a conformally formed gate dielectric and a gate conductor over the gate dielectric;
recessing the gate conductor to a position on the shaped spacer; and
etching the gate dielectric to a level of the gate conductor.

8. The method as recited in claim 7 , wherein forming the spacer form in the opening includes:
depositing a material in the opening; and
planarizing the material down to a top surface of the dielectric layer.

9. The method as recited in claim 8 , wherein the material includes amorphous carbon.

10. The method as recited in claim 7 , wherein etching the dielectric layer in the opening to form the contoured side walls includes etching a funnel-like shape in the dielectric layer.

11. The method as recited in claim 10 , wherein the spacer form takes the funnel-like shape in the dielectric layer.

12. The method as recited in claim 11 , wherein replacing the spacer form with the source/drain region grown on the fin includes forming the source/drain region with the funnel-like shape.

13. The method as recited in claim 7 , wherein the conformally formed gate dielectric and shaped spacers are disposed between the gate conductor and the source/drain region.

14. The method as recited in claim 7 , wherein the shaped spacer includes an annular configuration wherein the fin is disposed centrally within at least a portion of the shaped spacer and wherein the shaped spacer contacts the fin at the lower portion of the shaped spacer.

15. The vertical transistor as recited in claim 7 , wherein a wall of the shaped spacer includes an L-shaped profile.

16. A method for forming a vertical transistor, comprising:
forming a semiconductor fin with a cap thereon;
forming a first source/drain region below the fin;
depositing a dielectric layer around the fin and the cap;
removing the cap to form an opening in the dielectric layer over the fin;
etching the dielectric layer in the opening to form contoured side walls;
forming a spacer form in the opening;
recessing the dielectric layer to below the spacer form and to expose a portion of the fin;
forming a shaped spacer by depositing and etching a spacer material, the shaped spacer surrounding sides and a portion of a bottom of the spacer form;
replacing the spacer form with a second source/drain region grown on the fin;
removing the dielectric layer;
conformally forming a gate dielectric;
forming a gate conductor over the gate dielectric;
recessing the gate conductor to a position on the shaped spacer; and
etching the gate dielectric to a level of the gate conductor.

17. The method as recited in claim 16 , wherein forming the spacer form in the opening includes:
depositing a material in the opening; and
planarizing the material down to a top surface of the dielectric layer.

18. The method as recited in claim 17 , wherein the material includes amorphous carbon.

19. The method as recited in claim 16 , wherein etching the dielectric layer in the opening to form the contoured side walls includes etching a funnel-like shape in the dielectric layer to define a shape of the second source/drain region.

20. The method as recited in claim 16 , wherein the shaped spacer includes an annular configuration wherein the fin is disposed centrally within at least a portion of the shaped spacer and wherein the shaped spacer contacts the fin at the lower portion of the shaped spacer and a wall of the shaped spacer includes an L-shaped profile.

Assignees

• IBM

Inventors

• Wang Junli
• Cheng Kangguo
• Standaert Theodorus E
• Basker Veeraraghavan S

Classifications

• H01L29/7827

  Electricity · mapped topic

• H01L29/66666

  Electricity · mapped topic

• H01L29/42364

  Electricity · mapped topic

• H01L29/6656 Primary

  Electricity · mapped topic

• H10D64/514

  characterised by the insulating layers · CPC title