Stacked random-access-memory with complementary adjacent cells

Patent metadata

Field	Value
Publication number	US-12563715-B2
Application number	US-202217930096-A
Country	US
Kind code	B2
Filing date	Sep 7, 2022
Priority date	Sep 7, 2022
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

A field effect transistor (FET) cell structure of an integrated circuit (IC) is provided. The FET cell structure includes first and second adjacent cells. Each of the first and second adjacent cells spans a first layer and a second layer. The second layer is vertically stacked on the first layer. The first cell includes n-doped FETs (NFETs) on one of the first and second layers and p-doped FETs (PFETs) on another of the first and second layers. The second cell includes at least one of a number of NFETs on the one of the first and second layers differing from a number of the NFETs in the first cell and a number of PFETs on the another of the first and second layers differing from a number of the PFETs in the first cell.

First claim

What is claimed is:

1 . A field effect transistor (FET) cell structure of an integrated circuit (IC), the FET cell structure comprising:
first cells and second cells, each second cell being disposed adjacent to at least one of the first cells and each of the first and second cells spanning a first layer and a second layer vertically stacked on the first layer, each of the first cells comprising n-doped FETs (NFETs) on one of the first and second layers and p-doped FETs (PFETs) on another of the first and second layers, and each of the second cells comprising at least one of: a number of NFETs on the one of the first and second layers differing from a number of the NFETs in the first cell; and a number of PFETs on the another of the first and second layers differing from a number of the PFETs in the first cell, wherein, for each adjacent pair first and second cells: on one of the first and second layers, both opposite sides of the first cell extend beyond both corresponding opposite sides of the first cell on the other of the first and second layers and form first opposite facing steps, on the other one of the first and second layers, both opposite sides of the second cell extend beyond both corresponding opposite sides of the second cell on the one of the first and second layers and form second opposite facing steps, and complementary ones of the first opposite facing steps and the second opposite facing steps of the first and second cells are vertically complementary.

2 . The FET cell structure according to claim 1 , wherein a set of the NFETs of each of the first cells are NFET pass gates and a set of the PFETs of each of the second cells are PFET pass gates.

3 . The FET cell structure according to claim 1 , wherein each of the first cells has four NFETs and each of the second cells has two NFETs.

4 . The FET cell structure according to claim 3 , wherein each of the first cells has the four NFETs and two PFETs and each of the second cells has the two NFETs and four PFETs.

5 . The FET cell structure according to claim 1 , wherein the first cells and the second cells are of a same function type or are separately operable.

6 . The FET cell structure according to claim 1 , further comprising first and second bit lines having different bit line voltage pre-charge capabilities, the first bit line being associated with the first cells and the second bit line being associated with the second cells.

7 . The FET cell structure according to claim 1 , further comprising first and second bit lines, the first bit line being associated with a front side or a back side of the first cells and the second bit line being associated with the back side or the front side of the second cells.

8 . The FET cell structure according to claim 1 , further comprising first and second different word lines having different word line voltages, the first word line being associated with the first cells and the second word line being associated with the second cells.

9 . The FET cell structure according to claim 1 , wherein:
each adjacent pair of the first and second adjacent cells comprises one or more additional layers, and the first cells and the second cells each further comprise complementary numbers of NFETs and PFETs on the one or more additional layers.

10 . A field effect transistor (FET) cell structure of an integrated circuit (IC), the FET cell structure comprising:
first cells, each spanning a first layer and a second layer vertically stacked on the first layer, and second cells, each spanning the first layer and the second layer, the first cell comprising n-doped FETs (NFETs) on one of the first and second layers and p-doped FETs (PFETs) on another of the first and second layers, and the second cell comprising at least one of: a number of NFETs on the one of the first and second layers differing from a number of the NFETs in the first cell; and a number of PFETs on the another of the first and second layers differing from a number of the PFETs in the first cell; and additional electronic devices on the first and second layers and interposed between the first and second cells, the first and second cells and the additional electronic devices being vertically complementary, wherein, for each pair first and second cells with the additional electronic devices interposed therebetween: on one of the first and second layers, both opposite sides of the first cell extend beyond both corresponding opposite sides of the first cell on the other of the first and second layers and form first opposite facing steps, on the other one of the first and second layers, both opposite sides of the second cell extend beyond both corresponding opposite sides of the second cell on the one of the first and second layers and form second opposite facing steps, and complementary ones of the first opposite facing steps of the first cell and the corresponding one of the additional electronic devices and of the second opposite facing steps of the second cell and the corresponding one of the additional electronic devices are vertically complementary.

11 . The FET cell structure according to claim 10 , wherein the additional electronic devices are shared between the first and second cells.

Assignees

• IBM

Inventors

• Anderson Brent A
• Chu Albert M
• Wang Junli
• Radens Carl
• Xie Ruilong

Classifications

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H10B10/12

  comprising a MOSFET load element · CPC title

• G11C15/046

  using non-volatile storage elements · CPC title

• G11C11/412

  using field-effect transistors only · CPC title