Capacitors

Patent metadata

Field	Value
Publication number	US-10833149-B2
Application number	US-201916359292-A
Country	US
Kind code	B2
Filing date	Mar 20, 2019
Priority date	Jun 11, 2015
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

Back end of the line (BEOL) capacitors and methods of manufacture are provided. The method includes forming wiring lines on a substrate, with spacing between adjacent wiring lines. The method further includes forming an air gap within spacing between the adjacent wiring lines by deposition of a capping material. The method further includes opening the air gap between selected adjacent wiring lines. The method further includes depositing conductive material within the opened air gap.

First claim

What is claimed:

1. A semiconductor structure, comprising:
a back end of line capacitor comprising:
a bottom plate comprising a plurality of metal lines on an insulator layer;
a dielectric layer lining the metal lines; and
a top plate on the dielectric layer; and

an other metal line on the insulator layer, wherein a portion of the insulator layer extends between and contacts sidewalls of the other metal line and one of the plurality of metal lines, wherein the dielectric layer has a first thickness over the other metal line and the portion of the insulator layer, the dielectric layer has a second thickness over the plurality of metal lines, and the first thickness is different than the second thickness.

2. The semiconductor structure 1 , further comprising a second other metal line on the insulator layer, wherein the dielectric layer encloses an air gap between the other metal line and the second other metal line.

3. The semiconductor structure 1 , further comprising an etch stop layer.

4. The semiconductor structure 3 , wherein the insulator layer is on the etch stop layer.

5. The semiconductor structure 1 , wherein a top surface of the portion of the insulator layer contacts a bottom surface of the dielectric layer.

6. The semiconductor structure 1 , further comprising an insulator material on and over the dielectric layer.

7. The semiconductor structure 6 , wherein the top plate is formed in a trench in the insulator material.

8. The semiconductor structure 7 , wherein the trench extends into the dielectric layer.

9. The semiconductor structure 7 , further comprising a conductive material in another trench in the insulator material.

10. The semiconductor structure 9 , wherein the other trench extends only partially into the insulator material.

11. A method of forming a semiconductor structure, comprising:
forming a bottom plate comprising a plurality of metal lines on an insulator layer;
forming a dielectric layer lining the metal lines; and
forming a top plate on the dielectric layer; and
forming an other metal line on the insulator layer, wherein a portion of the insulator layer extends between and contacts sidewalls of the other metal line and one of the plurality of metal lines, wherein the dielectric layer has a first thickness over the other metal line and the portion of the insulator layer, the dielectric layer has a second thickness over the plurality of metal lines, and the first thickness is different than the second thickness.

12. The method of forming the semiconductor structure 11 , further comprising forming a second other metal line on the insulator layer, wherein the dielectric layer encloses an air gap between the other metal line and the second other metal line.

13. The method of forming the semiconductor structure 11 , further comprising forming an etch stop layer.

14. The method of forming the semiconductor structure 13 , wherein the insulator layer is on the etch stop layer.

15. The method of forming the semiconductor structure 11 , wherein a top surface of the portion of the insulator layer contacts a bottom surface of the dielectric layer.

16. The method of forming the semiconductor structure 11 , further comprising forming an insulator material on and over the dielectric layer.

17. The method of forming the semiconductor structure 16 , wherein the top plate is formed in a trench in the insulator material.

18. The method of forming the semiconductor structure 17 , wherein the trench extends into the dielectric layer.

19. The method of forming the semiconductor structure 17 , further comprising forming a conductive material in another trench in the insulator material.

20. The method of forming the semiconductor structure 19 , wherein the other trench extends only partially into the insulator material.

Assignees

• IBM

Inventors

• Basker Veeraraghavan S
• Cheng Kangguo
• Penny Christopher J
• Standaert Theodorus E
• Wang Junli

Classifications

• H10P50/283

  by chemical means · CPC title

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title