Self-aligned tunneling field effect transistors

Patent metadata

Field	Value
Publication number	US-10833180-B2
Application number	US-201816157518-A
Country	US
Kind code	B2
Filing date	Oct 11, 2018
Priority date	Oct 11, 2018
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

Semiconductor devices and methods of forming the same include forming a doped drain structure having a first conductivity type on sidewalls of an intrinsic channel layer. An opening is etched in a middle of the channel layer. A doped source structure is formed having a second conductivity type in the opening of the channel layer.

First claim

What is claimed is:

1. A method of forming a semiconductor device, comprising:
forming a doped drain structure having a first conductivity type on sidewalls of an intrinsic channel layer;
forming mandrel sidewalls over a dummy gate layer;
forming a dummy gate from the dummy gate layer, using the mandrel sidewalls as a mask, the dummy gate having a central opening that exposes a portion of the channel layer;
forming an opening in a middle of the channel layer after forming the doped drain structure, using the dummy gate as a mask;
forming a doped source structure having a second conductivity type in the opening of the channel layer.

2. The method of claim 1 , wherein forming the doped drain structure and the doped source structure comprises respective epitaxial growth processes that grow said structures from the channel layer.

3. The method of claim 1 , further comprising forming the dummy gate layer on the channel layer before forming the doped drain structure.

4. The method of claim 3 , further comprising forming a mandrel on the dummy gate layer, before forming the mandrel sidewalls, and anisotropically etching the dummy gate layer around the mandrel and mandrel sidewalls.

5. The method of claim 4 , wherein forming the opening in the middle of the channel layer comprises removing the mandrel from between the mandrel sidewalls and anisotropically etching the channel layer, using the dummy gate as a mask.

6. The method of claim 5 , further comprising forming a gate stack on the channel layer by etching away the sidewalls and the dummy gate and depositing a gate dielectric and a gate conductor.

7. The method of claim 3 , wherein forming the doped source structure comprises forming the doped source structure on sidewalls of the channel layer exposed by an anisotropic etch used to form the opening.

8. The method of claim 1 , wherein forming the doped drain structure comprises forming two such doped drain structures on respective sides of the channel layer.

9. The method of claim 1 , wherein the doped drain structure is formed from n-type doped indium arsenide, the channel layer is formed from intrinsic indium gallium arsenide, and the doped source structure is formed from p-type doped gallium antimonide.

10. The method of claim 1 , wherein the doped drain structure, the intrinsic channel layer, and the doped source structure are formed on a substrate formed from a material selected from the group consisting of a semi-insulating semiconductor material and a dielectric material.

11. The method of claim 1 , wherein forming the opening in the middle of the channel layer comprises anisotropically etching the opening, wherein the mask further comprises spacer structures formed over the dummy gate.

12. A method of forming a semiconductor device, comprising:
forming a first masking structure over a layer of indium gallium arsenide, the masking structure including a dummy gate layer and spacer structures over the dummy gate layer;
etching the layer of indium gallium arsenide to remove material around the masking structure and to form a channel layer thereby;
growing doped drain structures from n-type doped indium arsenide on respective sidewalls of the channel layer, over a substrate formed from a material selected from the group consisting of a semi-insulating semiconductor material and a dielectric material;
anisotropically etching an opening in the dummy gate layer, using the spacer structures as a mask, to form dummy gates;
anisotropically etching an opening in the channel layer using the dummy gates as a mask to expose the substrate and to form two channel structures;
growing a doped source structure from p-type doped gallium arsenide in the opening of the channel layer on sidewalls of the channel layer exposed by the anisotropic etch, wherein the doped source structure contacts both channel structures, forming two transistor devices that share the doped source structure.

13. The method of claim 12 , wherein forming the dummy gates comprises forming a mandrel with the sidewall structures on a layer of dummy gate material and anisotropically etching the dummy gate material around the mandrel and spacer structures.

14. The method of claim 13 , wherein etching the opening in the middle of the channel layer comprises removing the mandrel from between the spacer structures.

15. The method of claim 14 , further comprising forming a gate stack on the channel layer by etching away the spacer structures and the dummy gates and depositing a gate dielectric and a gate conductor.

16. A method of forming a semiconductor device, comprising:
forming a mask over an intrinsic semiconductor layer, the mask including a dummy gate layer and spacer structures over the dummy gate layer;
etching the semiconductor layer to remove semiconductor material around the mask and to form a channel layer thereby;
forming a doped drain structure having a first conductivity type on sidewalls of the channel layer;
etching an opening in the dummy gate layer, using the spacer structures as a mask, to form dummy gates;
etching an opening in a middle of the channel layer, using the dummy gates as a mask; and
forming a doped source structure having a second conductivity type in the opening of the channel layer.

17. The method of claim 16 , further comprising forming a dielectric liner on sidewalls of the spacer structures, the dummy gate layer, and the channel layer.

18. The method of claim 17 , wherein etching the opening in the dummy gate layer further comprises using the dielectric liner on the sidewalls of the spacer structures as part of the mask.

19. The method of claim 16 , further comprising forming a dielectric liner on sidewalls of the dummy gates.

20. The method of claim 19 , wherein etching the opening in the middle of the channel layer further comprises using the dielectric liner on the sidewalls of the dummy gates as part of the mask.

Assignees

• IBM

Inventors

• Song Yi
• Wang Junli
• Liu Chi-Chun
• Jiang Liying

Classifications

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P50/648

  Anisotropic liquid etching · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/824

  comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions · CPC title