Common self aligned gate contact for stacked transistor structures

Patent metadata

Field	Value
Publication number	US-12581702-B2
Application number	US-202217808566-A
Country	US
Kind code	B2
Filing date	Jun 24, 2022
Priority date	Jun 24, 2022
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

A stacked semiconductor structure including a top transistor stacked above a bottom transistor, and a single gate contact in electrical contact with a top gate conductor of the top transistor and a bottom gate conductor of the bottom transistor.

First claim

What is claimed is:

1 . A stacked semiconductor structure comprising:
a top transistor stacked above a bottom transistor; a single gate contact in electrical contact with a top gate conductor of the top transistor and a bottom gate conductor of the bottom transistor.

2 . The semiconductor structure according to claim 1 , wherein an uppermost surface of the top gate conductor is substantially flush with an uppermost surface of the single gate contact.

3 . The semiconductor structure according to claim 1 , wherein the top gate conductor and the single gate contact are only separated by a first barrier layer, a top work function metal layer, and a second barrier layer.

4 . The semiconductor structure according to claim 1 , further comprising:
a first barrier layer beneath the top gate conductor and above a top work function metal layer; and a second barrier layer beneath the single gate conductor, wherein first barrier layer and the second barrier layer are made from identical materials.

5 . The semiconductor structure according to claim 4 , wherein a sidewall of the top work function metal layer directly contacts a sidewall of the second barrier layer.

6 . The semiconductor structure according to claim 1 , further comprising:
a bonding oxide layer separating the bottom transistor from the top transistor, wherein the single gate contact extends through the bonding oxide layer.

7 . The semiconductor structure according to claim 1 , wherein the top transistor is a fin device and the bottom transistor is a nanosheet device.

8 . A stacked semiconductor structure comprising:
a top transistor stacked above a bottom transistor; a single gate contact in electrical contact with a top gate conductor of the top transistor and a bottom gate conductor of the bottom transistor, wherein the single gate contact is self-aligned to the top gate conductor.

9 . The semiconductor structure according to claim 8 , wherein an uppermost surface of the top gate conductor is substantially flush with an uppermost surface of the single gate contact.

10 . The semiconductor structure according to claim 8 , wherein the top gate conductor and the single gate contact are only separated by a first barrier layer, a top work function metal layer, and a second barrier layer.

11 . The semiconductor structure according to claim 8 , further comprising:
a first barrier layer beneath the top gate conductor and above a top work function metal layer; and a second barrier layer beneath the single gate conductor, wherein first barrier layer and the second barrier layer are made from identical materials.

12 . The semiconductor structure according to claim 11 , wherein a sidewall of the top work function metal layer directly contacts a sidewall of the second barrier layer.

13 . The semiconductor structure according to claim 8 , further comprising:
a bonding oxide layer separating the bottom transistor from the top transistor, wherein the single gate contact extends through the bonding oxide layer.

14 . The semiconductor structure according to claim 8 , wherein the top transistor is a fin device and the bottom transistor is a nanosheet device.

15 . A stacked semiconductor structure comprising:
a top transistor stacked above a bottom transistor; a single gate contact in electrical contact with a top gate conductor of the top transistor and a bottom gate conductor of the bottom transistor, wherein the top gate conductor and the single gate contact comprise the same conductive material.

16 . The semiconductor structure according to claim 15 , wherein an uppermost surface of the top gate conductor is substantially flush with an uppermost surface of the single gate contact.

17 . The semiconductor structure according to claim 15 , wherein the top gate conductor and the single gate contact are only separated by a first barrier layer, a top work function metal layer, and a second barrier layer.

18 . The semiconductor structure according to claim 15 , further comprising:
a first barrier layer beneath the top gate conductor and above a top work function metal layer; and a second barrier layer beneath the single gate conductor, wherein first barrier layer and the second barrier layer are made from identical materials.

19 . The semiconductor structure according to claim 18 , wherein a sidewall of the top work function metal layer directly contacts a sidewall of the second barrier layer.

20 . The semiconductor structure according to claim 15 , further comprising:
a bonding oxide layer separating the bottom transistor from the top transistor, wherein the single gate contact extends through the bonding oxide layer.

Assignees

• IBM

Inventors

• Fan Su Chen
• Sieg Stuart
• Liu Xuan
• Wang Junli

Classifications

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/6211

  having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/014

  of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors · CPC title