Vertical fin field effect transistor devices with a replacement metal gate

Patent metadata

Field	Value
Publication number	US-10679993-B2
Application number	US-201816182023-A
Country	US
Kind code	B2
Filing date	Nov 6, 2018
Priority date	Nov 6, 2018
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

A method of forming a fin field effect transistor complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a plurality of multilayer fin templates and vertical fins on a substrate, wherein one multilayer fin template is on each of the plurality of vertical fins. The method further includes forming a dummy gate layer on the substrate, the plurality of vertical fins, and the multilayer fin templates, and removing a portion of the dummy gate layer from the substrate from between adjacent pairs of the vertical fins. The method further includes forming a fill layer between adjacent pairs of the vertical fins. The method further includes removing a portion of the dummy gate layer from between the fill layer and the vertical fins, and forming a sidewall spacer layer on the fill layer and between the fill layer and the vertical fins.

First claim

What is claimed is:

1. A method of forming a fin field effect transistor complementary metal oxide semiconductor (CMOS) device, comprising:
forming a plurality of multilayer fin templates and vertical fins on a substrate, wherein one multilayer fin template is on each of the plurality of vertical fins;
forming a dummy gate layer on the substrate, the plurality of vertical fins, and the multilayer fin templates;
removing a portion of the dummy gate layer from the substrate from between adjacent pairs of the vertical fins;
forming a fill layer between adjacent pairs of the vertical fins;
removing a portion of the dummy gate layer from between the fill layer and the vertical fins; and
forming a sidewall spacer layer on the fill layer and between the fill layer and the vertical fins.

2. The method of claim 1 , further comprising removing a portion of the sidewall spacer layer to form sidewalls spacers between the fill layer and the vertical fins and expose a top surface of one or more of the plurality of vertical fins.

3. The method of claim 2 , further comprising forming top source/drains on the exposed top surfaces of the one or more of the plurality of vertical fins.

4. The method of claim 3 , further comprising removing the dummy gate layer from between the fill layer and the vertical fins to from a void space.

5. The method of claim 4 , further comprising forming a first replacement work function material in the void space.

6. The method of claim 5 , further comprising removing a portion of the fill layer to form an open space adjoining the first replacement work function material.

7. The method of claim 6 , further comprising forming a conductive gate fill in the open space form by removing the fill layer, wherein the conductive gate fill is in physical and electrical contact with the first replacement work function material.

8. The method of claim 7 , wherein the dummy gate layer is amorphous silicon (a-Si).

9. The method of claim 8 , wherein the dummy gate layer is formed by atomic layer deposition (ALD).

Assignees

• IBM

Inventors

• Bao Ruqiang
• Wang Junli
• Belyansky Michael P

Classifications

• H01L27/0924 Primary

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic

• H01L21/0217

  Electricity · mapped topic

• H01L29/6653

  Electricity · mapped topic

• H01L21/28525

  Electricity · mapped topic