Placeholder profile formation for backside contact

Patent metadata

Field	Value
Publication number	US-12568669-B2
Application number	US-202318314173-A
Country	US
Kind code	B2
Filing date	May 9, 2023
Priority date	May 9, 2023
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

Embodiments of present invention provide a method of forming backside contact. The method includes forming a set of gate stacks on top of a substrate; forming a first recess in the substrate between the set of gate stacks, the first recess having a triangle shape with a pointy bottom; forming a dielectric anchor at the pointy bottom of the first recess; with the dielectric anchor at the pointy bottom, performing a sigma etch of the substrate through the first recess to form a second recess; epitaxially growing a semiconductor material in the second recess to form a placeholder for a backside contact; surrounding the placeholder with a dielectric material; and replacing the placeholder with a conductive material to form the backside contact. The semiconductor structure formed thereby is also provided.

First claim

What is claimed is:

1 . A method comprising:
creating a first recess in a substrate, the first recess having a pointy bottom; forming a dielectric anchor at the pointy bottom of the first recess; performing a sigma etch of the substrate via the first recess while keeping the dielectric anchor at the pointy bottom of the first recess, thereby transforming the first recess into a second recess; and filling the second recess with a semiconductor material to form a placeholder.

2 . The method of claim 1 , wherein forming the dielectric anchor comprises:
depositing a conformal liner lining the first recess, wherein a portion of the conformal liner pinches off at the pointy bottom of the first recess; and performing an isotropic etch-back of the conformal liner, wherein the isotropic etch-back leaves the portion of the conformal liner that pinches off at the pointy bottom of the first recess substantially unetched to form the dielectric anchor while removing portions of the conformal liner above the dielectric anchor from the first recess.

3 . The method of claim 1 , wherein the second recess has a first set of facets adjacent to a top surface of the substrate and a second set of facets adjacent to the dielectric anchor, wherein the first and the second set of facets, when being measured vertically, have a first height and a second height respectively, and the first height of the first set of facets is greater than the second height of the second set of facets.

4 . The method of claim 3 , wherein the dielectric anchor at the pointy bottom of the first recess causes the sigma etch to slow down in areas near the dielectric anchor thereby causing the second recess to have the first and the second set of facets.

5 . The method of claim 1 , wherein the first recess has a triangle shape with the pointy bottom.

6 . The method of claim 1 , wherein performing the sigma etch does not cause the dielectric anchor to be removed from the first recess, and causes the dielectric anchor to remain at a bottom of the second recess.

7 . The method of claim 1 , wherein the placeholder comprises silicon-germanium (SiGe), further comprising replacing the placeholder with a conductive material to form a backside contact.

8 . The method of claim 7 , before replacing the placeholder, further comprising replacing the substrate with a dielectric layer and causing the placeholder to be embedded in the dielectric layer.

9 . The method of claim 1 , wherein the first recess is formed horizontally between a first gate stack and a second gate stack and in the substrate, wherein the first and the second gate stack are formed on top of the substrate.

10 . A method of forming backside contact comprising:
forming a set of gate stacks on top of a substrate; creating a first recess in the substrate between the set of gate stacks, the first recess having a triangle shape with a pointy bottom; forming a dielectric anchor at the pointy bottom of the first recess; with the dielectric anchor at the pointy bottom of the first recess, performing a sigma etch of the substrate through the first recess to form a second recess; epitaxially growing a semiconductor material in the second recess to form a placeholder for a backside contact; surrounding the placeholder with a dielectric material; and replacing the placeholder with a conductive material to form the backside contact.

11 . The method of claim 10 , wherein forming the dielectric anchor comprises:
depositing a conformal liner lining the first recess, a portion of the conformal liner pinching off at the pointy bottom of the first recess; and performing an isotropic etch-back of the conformal liner, the isotropic etch-back leaving the portion of the conformal liner at the pointy bottom substantially unetched to form the dielectric anchor while removing rest of the conformal liner from the first recess.

12 . The method of claim 10 , wherein the second recess has a first set of facets adjacent to a top surface of the substrate and a second set of facets adjacent to the dielectric anchor, and wherein, when being measured vertically, the first and the second set of facets have a first height and a second height respectively, and the first height of the first set of facets is greater than the second height of the second set of facets.

13 . The method of claim 12 , wherein the dielectric anchor causes the sigma etch to slow down in areas near the dielectric anchor thereby forming the first and the second set of facets.

14 . The method of claim 10 , wherein the first recess has a triangle shape below a top surface of the substrate, the triangle shape includes the pointy bottom.

Assignees

• IBM

Inventors

• Xie Ruilong
• Strane Jay William
• Wang Junli
• Chu Albert M
• Anderson Brent A

Classifications

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/6729

  characterised by the electrodes · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title

• H10D30/031

  of thin-film transistors [TFT] · CPC title