High density memory with stacked nanosheet transistors

Patent metadata

Field	Value
Publication number	US-12575113-B2
Application number	US-202217705320-A
Country	US
Kind code	B2
Filing date	Mar 26, 2022
Priority date	Mar 26, 2022
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

A high density memory apparatus includes a plurality of transistors vertically stacked on top of each other. The plurality of transistors share a common source structure, but each of the plurality of transistors has its own horizontal nanosheet and gate stack that are separate from respective horizontal channel structures and gate stacks of the others of the plurality of transistors. Ends of the nanosheets distal from the gate stacks are doped to act as drains for the transistors. Each of a plurality of two-terminal memory units is electrically connected to the drain end of a corresponding one of the nanosheets. Some embodiments achieve in excess of 5000 memory bits/square micrometer (μm 2 ); in some embodiments, in excess of 6000 bits/μm 2 .

First claim

What is claimed is:

1 . A high density memory apparatus, comprising:
a plurality of transistors vertically stacked on top of each other, wherein:
the plurality of transistors share a common source structure;
each of the plurality of transistors comprises its own horizontal nanosheet, and gate stack that are separate from respective horizontal channel structures and gate stacks of others of the plurality of transistors; and
drain ends of the nanosheets that are distal from the gate stacks are doped to act as drains for the transistors; and
a plurality of two-terminal memory units, each of which is electrically connected vertically above the drain end of a corresponding one of the nanosheets by a drain contact via; wherein:
each nanosheet protrudes in a horizontal first direction from the common source structure through its corresponding gate to its drain end;
from top to bottom of the stack of transistors, a metal portion of each gate stack protrudes from its corresponding nanosheet, in a horizontal second direction that is crosswise to the first direction, further than a metal portion of a next higher gate stack, so that a top gate metal is shorter than a bottom gate metal and so that gate contact vias of the plurality of transistors are horizontally offset from each other in the second direction along the lengths of the gate metals; and
from bottom to top of the stack of transistors, each lower nanosheet protrudes further in the first direction from its corresponding gate stack, compared to a next higher nanosheet, so that a bottom nanosheet is longer than a top nanosheet and the drain ends of the nanosheets are horizontally offset from each other in the first direction; and
wherein each gate metal protrudes no less than 20 nm further from the gate stacks, compared to a next higher gate metal.

2 . The apparatus of claim 1 , wherein each gate metal protrudes no more than 50 nm further from the gate stacks, compared to the next higher gate metal.

3 . The apparatus of claim 1 , wherein the two-terminal memory units comprise resistive memory units.

4 . The apparatus of claim 3 , wherein the resistive memory units comprise ovonic threshold switches.

5 . A high density memory apparatus, comprising:
a plurality of transistors vertically stacked on top of each other, wherein:
the plurality of transistors share a common source structure;
each of the plurality of transistors comprises its own horizontal nanosheet, and gate stack that are separate from respective horizontal channel structures and gate stacks of others of the plurality of transistors; and
drain ends of the nanosheets that are distal from the gate stacks are doped to act as drains for the transistors; and
a plurality of two-terminal memory units, each of which is electrically connected vertically above the drain end of a corresponding one of the nanosheets by a drain contact via; wherein:
each nanosheet protrudes in a horizontal first direction from the common source structure through its corresponding gate to its drain end;
from top to bottom of the stack of transistors, a metal portion of each gate stack protrudes from its corresponding nanosheet, in a horizontal second direction that is crosswise to the first direction, further than a metal portion of a next higher gate stack, so that a top gate metal is shorter than a bottom gate metal and so that gate contact vias of the plurality of transistors are horizontally offset from each other in the second direction along the lengths of the gate metals; and
from bottom to top of the stack of transistors, each lower nanosheet protrudes further in the first direction from its corresponding gate stack, compared to a next higher nanosheet, so that a bottom nanosheet is longer than a top nanosheet and the drain ends of the nanosheets are horizontally offset from each other in the first direction; and
wherein each nanosheet protrudes no less than 20 nm further from the gate stacks, compared to a next higher nanosheet structure.

6 . The apparatus of claim 5 , wherein each nanosheet protrudes no more than 50 nm further from the gate stacks, compared to the next higher nanosheet structure.

7 . A high density memory apparatus, comprising:
a plurality of transistors vertically stacked on top of each other, wherein:
the plurality of transistors share a common source structure;
each of the plurality of transistors comprises its own horizontal nanosheet, and gate stack that are separate from respective horizontal channel structures and gate stacks of others of the plurality of transistors; and
drain ends of the nanosheets that are distal from the gate stacks are doped to act as drains for the transistors; and
a plurality of two-terminal memory units, each of which is electrically connected vertically above the drain end of a corresponding one of the nanosheets by a drain contact via; wherein:
each nanosheet protrudes in a horizontal first direction from the common source structure through its corresponding gate to its drain end;
from top to bottom of the stack of transistors, a metal portion of each gate stack protrudes from its corresponding nanosheet, in a horizontal second direction that is crosswise to the first direction, further than a metal portion of a next higher gate stack, so that a top gate metal is shorter than a bottom gate metal and so that gate contact vias of the plurality of transistors are horizontally offset from each other in the second direction along the lengths of the gate metals; and
from bottom to top of the stack of transistors, each lower nanosheet protrudes further in the first direction from its corresponding gate stack, compared to a next higher nanosheet, so that a bottom nanosheet is longer than a top nanosheet and the drain ends of the nanosheets are horizontally offset from each other in the first direction; and
wherein lengths of the nanosheets and the gate metals are such as to achieve in excess of 5000 memory bits/square micrometer (μm2).

8 . The apparatus of claim 7 , wherein the lengths of the nanosheets and the gate metals are such as to achieve in excess of 6000 bits/μm2.

9 . A high density transistor apparatus comprising:
a plurality of transistors vertically stacked on top of each other, wherein:
the plurality of transistors share a common source structure;
each of the plurality of transistors comprises its own horizontal nanosheet and gate stack that are separate from others of the plurality of transistors;
each nanosheet protrudes in a horizontal first direction from the common source structure through its corresponding gate to a corresponding drain end that is doped to act as a drain; and
from bottom to top of the stack of transistors, a metal portion of each lower gate stack protrudes from its corresponding nanosheet, in a horizontal second direction that is crosswise to the first direction, further than a metal portion of a next higher gate stack, so that a top gate metal is shorter than a bottom gate metal and so that gate contact vias of the plurality of transistors are horizontally offset from each other in the second direction along the lengths of the gate metals;
wherein: each nanosheet protrudes in a horizontal first direction from the common source structure through its corresponding gate to its drain end; from bottom to top of the stack of transistors, each lower nanosheet protrudes further in the first direction from its corresponding gate stack, compared to a next higher nanosheet, so that a bottom nanosheet is longer than a top nanosheet and the drain ends of the nanosheets are horizontally offset from each other in the first direction; and each gate metal protrudes no less than 20 nm further from the gate stacks, compared

Assignees

• IBM

Inventors

• Wu Heng
• Yamashita Tenko
• Mehta Sanjay C
• Wang Junli

Classifications

• H10B63/84

  arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays · CPC title

• H10B63/30 Primary

  comprising selection components having three or more electrodes, e.g. transistors · CPC title