Two-terminal reversibly switchable memory device
US-11672189-B2 · Jun 6, 2023 · US
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Rinerson Darrell patents
Rinerson Darrell is listed as an inventor on 32 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Rinerson Darrell |
| Total patents | 32 |
| First publication | Jan 29, 2015 |
| Latest publication | Jun 6, 2023 |
Notable patents
Publications ranked by popularity score, then publication date.
Memory element with a reactive metal layer
US-11502249-B2 · Nov 15, 2022 · US
Local bit lines and methods of selecting the same to access memory elements in cross-point arrays
US-11398256-B2 · Jul 26, 2022 · US
Two-terminal reversibly switchable memory device
US-11063214-B2 · Jul 13, 2021 · US
Two-terminal reversibly switchable memory device
US-2021193917-A1 · Jun 24, 2021 · US
Memory element with a reactive metal layer
US-2021013262-A1 · Jan 14, 2021 · US
Memory element with a reactive metal layer
US-10833125-B2 · Nov 10, 2020 · US
Local bit lines and methods of selecting the same to access memory elements in cross-point arrays
US-2020302973-A1 · Sep 24, 2020 · US
Two-terminal reversibly switchable memory device
US-2020259079-A1 · Aug 13, 2020 · US
Two-terminal reversibly switchable memory device
US-10680171-B2 · Jun 9, 2020 · US
Recent patents
Latest publications not already listed above.
Local bit lines and methods of selecting the same to access memory elements in cross-point arrays
US-10622028-B2 · Apr 14, 2020 · US
Memory element with a reactive metal layer
US-2019305047-A1 · Oct 3, 2019 · US
Memory element with a reactive metal layer
US-10340312-B2 · Jul 2, 2019 · US
Two-terminal reversibly switchable memory device
US-2019173006-A1 · Jun 6, 2019 · US
Two-terminal reversibly switchable memory device
US-10224480-B2 · Mar 5, 2019 · US
Local bit lines and methods of selecting the same to access memory elements in cross-point arrays
US-2018342268-A1 · Nov 29, 2018 · US
Local bit lines and methods of selecting the same to access memory elements in cross-point arrays
US-10002646-B2 · Jun 19, 2018 · US
Two-terminal reversibly switchable memory device
US-2018130946-A1 · May 10, 2018 · US
Memory element with a reactive metal layer
US-2018122857-A1 · May 3, 2018 · US
Low read current architecture for memory
US-9837149-B2 · Dec 5, 2017 · US
Two-terminal reversibly switchable memory device
US-9831425-B2 · Nov 28, 2017 · US
Memory element with a reactive metal layer
US-9806130-B2 · Oct 31, 2017 · US
Memory element with a reactive metal layer
US-2017179197-A1 · Jun 22, 2017 · US
Memory element with a reactive metal layer
US-9570515-B2 · Feb 14, 2017 · US
Low read current architecture for memory
US-2016372189-A1 · Dec 22, 2016 · US
Low read current architecture for memory
US-9368200-B2 · Jun 14, 2016 · US
Memory element with a reactive metal layer
US-2016005793-A1 · Jan 7, 2016 · US
Two-terminal reversibly switchable memory device
US-2015380642-A1 · Dec 31, 2015 · US
Memory element with a reactive metal layer
US-9159408-B2 · Oct 13, 2015 · US
Two-terminal reversibly switchable memory device
US-9159913-B2 · Oct 13, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Unity Semiconductor Corp | 20 |
| Hefei Reliance Memory Ltd | 12 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C13/0069 | 32 |
| G11C13/0007 | 32 |
| G11C13/004 | 32 |
| H10B63/84 | 29 |
| G11C2213/71 | 26 |