Low read current architecture for memory

Patent metadata

Field	Value
Publication number	US-9368200-B2
Application number	US-201414254209-A
Country	US
Kind code	B2
Filing date	Apr 16, 2014
Priority date	Jul 26, 2007
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a plurality of bit lines;
a plurality of word lines;
a plurality of re-writeable non-volatile resistive state memory elements (ME's), each ME is positioned at an intersection of one of the word lines with one of the bit lines, each ME comprising a first terminal electrically coupled with its respective word line and a second terminal electrically coupled with its respective bit line, and each ME is to store at least one-bit of non-volatile data;
pre-charge circuitry to apply a first voltage to the plurality of bit lines;
word line circuitry to apply a second voltage to a selected word line of the plurality of word lines and to apply the first voltage to an unselected remainder of the plurality of word lines;
a reference cell comprising a first terminal electrically coupled with a reference bit line and a second terminal electrically coupled with the selected word line; and
multi-sensing read circuitry coupled to the plurality of bit lines and the reference bit line, the multi-sensing read circuitry to:
simultaneously sense a voltage change during a sensing window of more than one bit line of the plurality of bit lines using a respective plurality of sense amplifiers responsive to applying the second voltage to the selected word line and applying the first voltage to the unselected word lines; and
output read data indicative of the current on each of the more than one bit lines, respectively, responsive to simultaneously sensing the more than one bit line of the plurality of bit lines using the plurality of sense amplifiers.

2. An integrated circuit, comprising:
a plurality of bit lines;
a plurality of word lines;
a plurality of re-writeable non-volatile resistive state memory elements (ME's), each ME is positioned at an intersection of one of the word lines with one of the bit lines, each ME comprising a first terminal electrically coupled with its respective word line and a second terminal electrically coupled with its respective bit line, and each ME is to store at least one-bit of non-volatile data;
pre-charge circuitry to apply a first voltage to the plurality of bit lines; and
word line circuitry to apply a second voltage to one of the plurality of word lines and to apply the first voltage to a remainder of the plurality of word lines, wherein the word line having the second voltage applied to it is a selected word line and the word lines having the first voltage applied to them are un-selected word lines;
a reference cell comprising a first terminal electrically coupled with a reference bit line and a second terminal electrically coupled with the selected word line; and
sensing circuitry coupled to the plurality of bit lines, the sensing circuitry comprising at least a plurality of sense amplifiers coupled to the plurality of bit lines, the sensing circuitry to:
simultaneously sense a voltage change during a sensing window of more than one bit line of the plurality of bit lines using, respectively, more than one of the sense amplifiers responsive to applying the second voltage to the selected word line and applying the first voltage to the unselected word lines; and
output read data indicative of the current on each of the more than one bit lines, respectively, responsive to simultaneously sensing the more than one bit line of the plurality of bit lines using, respectively, the more than one of the sense amplifiers.

3. The integrated circuit of claim 2 and further comprising:
a plurality of reference cells, each reference cell comprising a first terminal electrically coupled with a reference bit line and a second terminal electrically coupled with one of the plurality of word lines, wherein the reference bit line is coupled to each sense amplifier of the plurality of sense amplifiers.

4. The integrated circuit of claim 3 , wherein each reference cell is programmed to a resistance value that is a weighted average of a first resistance value indicative of a logic “0” state and a second resistance value indicative of a logic “1” state.

5. The integrated circuit of claim 3 , wherein each reference cell is programmed to a resistance value that is a percentage of a first resistance value indicative of a logic “0” state.

6. The integrated circuit of claim 3 , wherein each reference cell is programmed to a resistance value that is a percentage of a second resistance value indicative of a logic “1” state.

7. The integrated circuit of claim 3 , wherein each reference cell is programmed to a resistance value other than a first resistance value indicative of a logic “0” state a second resistance value indicative of a logic “1” state, or a midpoint resistance value that is approximately mid-way between the first resistance value and the second resistance value.

8. The integrated circuit of claim 2 , wherein the reference cell comprises a structure that is identical to a structure of each ME.

9. The integrated circuit of claim 3 and further comprising: a reference voltage electrically coupled to each sense amplifier of the plurality of sense amplifiers, the reference voltage indicative of a resistance value of one or more of the plurality of reference cells.

10. The integrated circuit of claim 2 , wherein the plurality of re-writeable nonvolatile resistive state memory elements comprise phase change memory elements.

11. The integrated circuit of claim 2 , wherein the plurality of re-writeable nonvolatile resistive state memory elements comprise conductive bridge memory elements.

12. The integrated circuit of claim 2 , wherein the plurality of re-writeable nonvolatile resistive state memory elements comprise filamentary memory elements.

13. The integrated circuit of claim 2 , wherein the plurality of re-writeable nonvolatile resistive state memory elements comprise MEMRISTOR memory elements.

14. The integrated circuit of claim 2 , wherein the plurality of re-writeable nonvolatile resistive state memory elements comprise memristive memory elements.

15. The integrated circuit of claim 2 , wherein the plurality of re-writeable nonvolatile resistive state memory elements comprise a memory element utilizing mobile metal ion motion to change resistive states.

16. The integrated circuit of claim 2 , wherein the plurality of re-writeable nonvolatile resistive state memory elements comprise a memory element comprising at least one tunneling layer that is electrically in series with or is in contact with an ion reservoir.

17. The integrated circuit of claim 2 and further comprising: a non-ohmic device (NOD) electrically in series with each ME and its respective word and bit lines.

18. An integrated circuit, comprising:
a plurality of bit lines;
a plurality of word lines;
a plurality of re-writeable non-volatile resistive state memory elements (ME's), each ME is positioned at an intersection of one of the word lines with one of the bit lines, each ME comprising a first terminal electrically coupled with its respective word line and a second terminal electrically coupled with its respective bit line, and each ME is to store at least one-bit of non-volatile data;
pre-charge circuitry to apply a first voltage to the plurality of bit lines;
word line circuitry to apply a second voltage to only one of the plurality of word lines and to apply the first voltage to a remainder of the plurality of word lines, wherein the word line having the second voltage applied to it is a selected word line and the word lines having the first voltage applied to them are un-selected word lines;
a reference cell compr

Assignees

• Unity Semiconductor Corp

Inventors

• Bateman Bruce Lynn
• Chevallier Christophe
• Rinerson Darrell
• Siau Chang Hua

Classifications

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C13/0028

  Word-line or row circuits · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C13/0061

  Timing circuits or methods · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title