Memory element with a reactive metal layer

Patent metadata

Field	Value
Publication number	US-11502249-B2
Application number	US-202017028909-A
Country	US
Kind code	B2
Filing date	Sep 22, 2020
Priority date	Feb 6, 2004
Publication date	Nov 15, 2022
Grant date	Nov 15, 2022

Abstract

A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.

First claim

What is claimed is:

1. A memory plug comprising:
a multi-resistive state element, wherein the multi-resistive state element comprises:
a conductive layer; and
a reactive metal that reacts with the conductive layer, wherein the memory plug is capable of reversibly switching from a first resistive state to a second resistive state.

2. The memory plug of claim 1 , wherein the reactive metal is fully reacted with the conductive layer.

3. The memory plug of claim 1 , wherein the memory plug is exposed to a range of voltages without disturbing the resistive states of the memory plug.

4. The memory plug of claim 1 , further comprising:
at least two electrodes.

5. The memory plug of claim 4 , wherein at least one of the at least two electrodes is Pt.

6. The memory plug of claim 1 , wherein the conductive layer is a conductive metal oxide.

7. The memory plug of claim 1 , wherein the reactive metal is one or more of Al, Ti, Mg, W, Fe, Cr, Vn, Zn, Ta or Mo.

8. The memory plug of claim 1 , wherein the multi-resistive state element has a non-ohmic characteristic such that the multi-resistive state element exhibits:
a high resistance regime for a range of voltages; and
a resistance indicative of the first resistive state or the second resistive state for voltages outside of the range of voltages.

9. The memory plug of claim 8 , further comprising:
a non-ohmic device coupled in series with the multi-resistive state element, wherein the non-ohmic device is configured to operatively effectuate the non-ohmic characteristic.

10. The memory plug of claim 9 , wherein the non-ohmic device includes the reactive metal.

11. The memory plug of claim 8 , further comprising:
an integrated non-ohmic device coupled in series with the multi-resistive state element, wherein the integrated non-ohmic device is configured to operatively effectuate the non-ohmic characteristic.

12. The memory plug of claim 11 , wherein the integrated non-ohmic device includes the reactive metal.

13. The memory plug of claim 1 , wherein the memory plug is non-volatile such that the first resistive state or the second resistive state is retained in absence of power.

14. The memory plug of claim 1 , wherein a thickness of the reactive metal is less than 200 Angstroms.

15. The memory plug of claim 14 , wherein the thickness of the reactive metal is less than 100 Angstroms.

16. The memory plug of claim 1 , wherein the reactive metal is annealed.

17. A memory cell comprising:
a memory plug comprising:
a multi-resistive state element, wherein the multi-resistive state element comprises:
a conductive layer, and
a reactive metal that reacts with the conductive layer, the memory plug being capable of reversibly switching from a first resistive state to a second resistive state;

an electrode; and
a transistor configured to permit current from the electrode to access the memory plug when a voltage is applied to a gate of the transistor.

18. The memory cell of claim 17 , wherein the reactive metal is fully reacted with the conductive layer.

19. The memory cell of claim 17 , wherein the memory plug can be exposed to a range of voltages without disturbing the first resistive state of the memory plug.

Assignees

• Hefei Reliance Memory Ltd

Inventors

• Chevallier Christophe J
• Hsia Steve Kuo-Ren
• Kinney Wayne
• Longcor Steven
• Rinerson Darrell
• Sanchez John
• Swab Philip F S
• Ward Edmond R

Classifications

• G11C2013/009

  Write using potential difference applied between cell electrodes · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title

• G11C11/16

  using elements in which the storage effect is based on magnetic spin effect · CPC title

• G11C2213/71

  Three dimensional array · CPC title