Memory element with a reactive metal layer

US9570515B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9570515-B2
Application numberUS-201514850702-A
CountryUS
Kind codeB2
Filing dateSep 10, 2015
Priority dateFeb 6, 2004
Publication dateFeb 14, 2017
Grant dateFeb 14, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO 3 -LSCoO or LaNiO 3 -LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.

First claim

Opening claim text (preview).

What is claimed is: 1. A re-writeable non-volatile memory device, comprising: a re-writeable non-volatile two-terminal memory element (ME) comprising tantalum, the ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer, the second layer and the first layer operative to store at least one-bit of data as a plurality of resistive states, the first and second layer are electrically in series with each other and with the first and second terminals, wherein the first layer includes a first lattice structure and the second layer includes a second lattice structure that substantially matches the first lattice structure. 2. The re-writeable non-volatile memory device of claim 1 , wherein the second layer comprises Al, Ti, Mg, W, Fe, Cr, V, Zn, Ta or Mo. 3. The re-writeable non-volatile memory device of claim 1 , wherein the second layer comprises reactive metal or has a thickness that is approximately 200 Angstroms or less. 4. The re-writeable non-volatile memory device of claim 1 and further comprising: an integral non-ohmic device (NOD) created by the direct contact between the first and second layers, the integral NOD is electrically in series with the ME and with the first and second terminals. 5. A re-writeable non-volatile memory device, comprising: a re-writeable non-volatile two-terminal memory element (ME) comprising tantalum, the ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer, the second layer and the first layer operative to store at least one-bit of data as a plurality of resistive states, the first and second layer are electrically in series with each other and with the first and second terminals, wherein the direct contact between the first layer and the second layer is operative to impart a non-linear I-V characteristic to the ME. 6. The re-writeable non-volatile memory device of claim 5 , wherein the ME includes the non-linear I-V characteristic for both a programming voltage applied across the first and second terminals and an erase voltage applied across the first and second terminals. 7. The re-writeable non-volatile memory device of claim 5 , wherein the ME includes the non-linear I-V characteristic that is non-linear in both a positive quadrant and a negative quadrant of the non-linear I-V characteristic. 8. The re-writeable non-volatile memory device of claim 5 and further comprising: a non-ohmic device (NOD) electrically in series with the ME and the first and second terminals. 9. The re-writeable non-volatile memory device of claim 5 , wherein the tantalum is of a compound, wherein the compound comprises tantalum oxide. 10. The re-writeable non-volatile memory device of claim 9 , wherein the tantalum oxide comprises at least one of tantalum pentoxide or ruthenium tantalum oxide. 11. The re-writeable non-volatile memory device of claim 5 , wherein the tantalum is of a ternary oxide, the ternary oxide comprising at least one of ruthenium or iridium. 12. The re-writeable non-volatile memory device of claim 5 , wherein at least a portion of the tantalum of the ME is located in the first layer. 13. The re-writeable non-volatile memory device of claim 5 , wherein at least a portion of the tantalum of the ME is located in the second layer. 14. A re-writeable non-volatile memory device, comprising: a re-writeable non-volatile two-terminal memory element (ME) comprising tantalum, the ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer, the second layer and the first layer operative to store at least one-bit of data as a plurality of resistive states, the first and second layer are electrically in series with each other and with the first and second terminals, wherein the re-writeable non-volatile two-terminal memory element is positioned between a cross-point of a first conductive array line with a second conductive array line, the re-writeable non-volatile two-terminal memory element includes a first terminal directly electrically coupled with the first conductive array line and a second terminal directly electrically coupled with the second conductive array line, and wherein the re-writeable non-volatile two-terminal memory element is directly electrically in series with its respective first and second conductive array lines. 15. The re-writeable non-volatile memory device of claim 14 , wherein the CMO comprises a perovskite. 16. The re-writeable non-volatile memory device of claim 14 and further comprising: a two-terminal cross-point array including: a plurality of the first conductive array lines, a plurality of the second conductive array lines, and a plurality of the re-writeable non-volatile two-terminal memory elements, and wherein each re-writeable non-volatile two-terminal memory element is positioned between the cross-point of one of the plurality of the first conductive array lines with one of the plurality of the second conductive array lines. 17. The re-writeable non-volatile memory device of claim 16 , wherein the plurality of first and second conductive array lines are electrically coupled with front-end-of-the-line (FEOL) active circuitry fabricated on a semiconductor substrate, the two-terminal cross-point array is in contact with the semiconductor substrate and is fabricated directly above the semiconductor substrate, and at least a portion of the FEOL active circuitry configured to access at least one of the re-writeable non-volatile two-terminal memory elements for read operations, write operations, or both read and write operations. 18. The re-writeable non-volatile memory device of claim 17 , wherein the two-terminal cross-point array comprises a stacked cross-point array including a plurality of memory layers. 19. The re-writeable non-volatile memory device of claim 3 , wherein the second layer has a thickness that is in the order of tens of Angstroms.

Assignees

Inventors

Classifications

  • Material having complex metal oxide, e.g. perovskite structure · CPC title

  • Material having simple binary metal oxide structure · CPC title

  • Three dimensional array · CPC title

  • Reading or sensing circuits or methods · CPC title

  • using storage elements comprising metal oxide memory material, e.g. perovskites · CPC title

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What does patent US9570515B2 cover?
A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductiv…
Who is the assignee on this patent?
Unity Semiconductor Corp
What technology area does this patent fall under?
Primary CPC classification G11C11/5685. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Feb 14 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).