Low read current architecture for memory

Patent metadata

Field	Value
Publication number	US-2016372189-A1
Application number	US-201615181009-A
Country	US
Kind code	A1
Filing date	Jun 13, 2016
Priority date	Jul 26, 2007
Publication date	Dec 22, 2016
Grant date	—

Abstract

A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.

First claim

1 . (canceled)

2 . An integrated circuit, comprising:
a plurality of bit lines; a plurality of word lines; a plurality of re-writeable non-volatile resistive state memory elements, each memory element positioned at an intersection of one of the word lines with one of the bit lines; word line circuitry to apply a first voltage to one of the plurality of word lines and to apply a second voltage to a remainder of the plurality of word lines, wherein the word line having the first voltage applied to it is a selected word line and the word lines having the second voltage applied to them are un-selected word lines; a reference cell comprising a first terminal electrically coupled with a reference bit line and a second terminal electrically coupled with the selected word line; and sensing circuitry coupled to the plurality of bit lines and the reference bit line, the sensing circuitry to:
sense a voltage change of a bit line of the plurality of bit lines using a sense amplifier, wherein the sense amplifier is coupled to the reference bit line and the bit line of the plurality of bit lines; and
output read data indicative of the current on the bit line of the plurality of bit lines, responsive to sensing the voltage change of the bit line of the plurality of bit lines.

3 . The integrated circuit of claim 2 , wherein the sensing circuitry comprises a plurality of sense amplifiers and the reference cell is electrically coupled to each sense amplifier of the plurality of sense amplifiers.

4 . The integrated circuit of claim 2 , further comprising a plurality of additional reference cells, each reference cell comprising a first terminal electrically coupled with a reference bit line and a second terminal electrically coupled with one of the plurality of word lines, wherein the reference bit line is coupled to each sense amplifier of the plurality of sense amplifiers.

5 . The integrated circuit of claim 2 , wherein the reference cell is programmed to a resistance value that is a weighted average of a first resistance value indicative of a logic “0” state and a second resistance value indicative of a logic “1” state.

6 . The integrated circuit of claim 2 , wherein the reference cell is programmed to a resistance value other than a first resistance value indicative of a logic “0” state, a second resistance value indicative of a logic “1” state, or other than a midpoint resistance value that is approximately mid-way between the first resistance value and the second resistance value.

7 . The integrated circuit of claim 2 , wherein the reference cell has a structure of a memory element programmed to an intermediate resistance.

8 . The integrated circuit of claim 2 , wherein the plurality of memory elements comprise: phase change memory elements, conductive bridge memory elements, filamentary memory elements, MEMRISTOR memory elements, memristive memory elements, memory elements utilizing mobile metal ion motion to change resistive states, or a tunneling layer that is electrically in series with or is in contact with an ion reservoir.

9 . The integrated circuit of claim 2 , wherein the reference cell comprises a phase change memory element, a conductive bridge memory element, a filamentary memory element, a MEMRISTOR memory element, a memristive memory element, a memory element utilizing mobile metal ion motion to change resistive states, or a tunneling layer that is electrically in series with or is in contact with an ion reservoir.

10 . An integrated circuit, comprising:
a plurality of bit lines; a plurality of word lines; a plurality of re-writeable non-volatile resistive state memory elements; a plurality of reference cells, each reference cell comprising a first terminal electrically coupled with a reference bit line and a second terminal electrically coupled with one of the plurality of word lines; and sensing circuitry coupled to the plurality of bit lines and the reference bit line, the sensing circuitry to sense a voltage change of a bit line of the plurality of bit lines using a sense amplifier, wherein the sense amplifier is coupled to the reference bit line and the bit line of the plurality of bit lines.

11 . The integrated circuit of claim 10 , wherein the sensing circuitry is further to output read data indicative of the current on the bit line of the plurality of bit lines, responsive to sensing the voltage change of the bit line of the plurality of bit lines.

12 . The integrated circuit of claim 10 , further comprising word line circuitry to apply a first voltage to one of the plurality of word lines and to apply a second voltage to a remainder of the plurality of word lines, wherein the word line having the first voltage applied to it is the selected word line and the word lines having the second voltage applied to them are un-selected word lines.

13 . The integrated circuity of the claim 10 , wherein the sensing circuitry comprises a plurality of sense amplifiers and the plurality of reference cells are electrically coupled to each sense amplifier of the plurality of sense amplifiers.

14 . The integrated circuit of claim 10 , wherein the plurality of reference cells are programmed to a resistance value that is a weighted average of a first resistance value indicative of a logic “0” state and a second resistance value indicative of a logic “1” state.

15 . The integrated circuit of claim 10 , wherein the plurality of reference cells are programmed to a resistance value other than a first resistance value indicative of a logic “0” state, a second resistance value indicative of a logic “1” state, or other than a midpoint resistance value that is approximately mid-way between the first resistance value and the second resistance value.

16 . The integrated circuit of claim 10 , wherein the plurality of reference cells have a structure of a memory element programmed to an intermediate resistance.

17 . The integrated circuit of claim 10 , wherein the plurality of reference cells: phase change memory elements, conductive bridge memory elements, filamentary memory elements, MEMRISTOR memory elements, memristive memory elements, memory elements utilizing mobile metal ion motion to change resistive states, or a tunneling layer that is electrically in series with or is in contact with an ion reservoir.

18 . A method comprising:
applying a first voltage to a reference cell comprising a first terminal electrically coupled with a reference bit line and a second terminal electrically coupled with a selected word line; sensing, with sensing circuitry, a voltage change of a bit line of a plurality of bit lines using a sense amplifier, wherein the sense amplifier is coupled to the reference bit line and the bit line of the plurality of bit lines; and outputting read data indicative of the current on the bit line of the plurality of bit lines, responsive to sensing the voltage change of the bit line of the plurality of bit lines.

19 . The method of claim 18 , further comprising applying, with word line circuitry a first voltage to one of the plurality of word lines and to apply a second voltage to a remainder of the plurality of word lines, wherein the word line having the first voltage applied to it is a selected word line and the word lines having the second voltage applied to them are un-selected word lines.

20 . The method of claim 18 , wherein the sensing circuitry comprises a plurality of sense amplifiers and the reference cell is electrically coupled to each sense amplifier of the plurality of sense amp

Assignees

• Unity Semiconductor Corp

Inventors

• Bateman Bruce Lynn
• Chevallier Christophe
• Rinerson Darrell
• Siau Chang Hua

Classifications

• G11C13/0009

  RRAM elements whose operation depends upon chemical change · CPC title

• G11C13/0061

  Timing circuits or methods · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title