Memory element with a reactive metal layer

US9806130B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9806130-B2
Application numberUS-201615393545-A
CountryUS
Kind codeB2
Filing dateDec 29, 2016
Priority dateFeb 6, 2004
Publication dateOct 31, 2017
Grant dateOct 31, 2017

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Abstract

Official abstract text for this publication.

A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.

First claim

Opening claim text (preview).

What is claimed is: 1. A re-writeable non-volatile memory device, comprising: a re-writeable non-volatile two-terminal memory element (ME) comprising a first transition metal, the ME comprising: a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer of reactive metal in direct contact with the first layer, the second layer and the first layer operative to store at least one-bit of data as a plurality of resistive states, wherein the first and second layer are electrically in series with each other and with the first and second terminals. 2. The re-writeable non-volatile memory device of claim 1 , wherein the first transition metal comprises tantalum. 3. The re-writeable non-volatile memory device of claim 1 , wherein the first transition metal comprises titanium. 4. The re-writeable non-volatile memory device of claim 1 , wherein first layer comprises the first transition metal. 5. The re-writeable non-volatile memory device of claim 1 , wherein the second layer comprises the first transition metal. 6. The re-writeable non-volatile memory device of claim 1 , wherein the second layer comprises a second transition metal being different than the first transition metal. 7. The re-writeable non-volatile memory device of claim 1 , wherein the ME is crystalline. 8. The re-writeable non-volatile memory device of claim 1 , wherein the ME comprises a combination of materials including the first transition metal. 9. The re-writeable non-volatile memory device of claim 8 , wherein the combination of materials includes materials different than the first transition metal. 10. A method of fabricating a re-writeable non-volatile memory device comprising a first transition metal, the method comprising: forming a first terminal; forming a second terminal; forming a first layer of a conductive metal oxide (CMO); and forming a second layer of reactive metal in direct contact with the first layer, the second layer and the first layer operative to store at least one-bit of data as a plurality of resistive states, wherein the first and second layer are electrically in series with each other and with the first and second terminals. 11. The method of claim 10 , wherein the first transition metal comprises tantalum. 12. The method of claim 10 , wherein the first transition metal comprises titanium. 13. The method of claim 10 , wherein first layer comprises the first transition metal. 14. The method of claim 10 , wherein the second layer comprises the first transition metal. 15. The method of claim 10 , wherein the second layer comprises a second transition metal being different than the first transition metal. 16. The method of claim 10 , wherein the ME is crystalline. 17. The method of claim 10 , wherein the ME comprises a combination of materials including the first transition metal. 18. The method of claim 17 , wherein the combination of materials includes materials different than the first transition metal. 19. The method of claim 10 , wherein the forming of the first and second layers are performed through deposition. 20. The method of claim 19 , where the deposition is performed using processing at temperature above 400° C. 21. The re-writeable non-volatile memory device of claim 1 , wherein the reactive metal of the second layer creates a differential between a first resistive state and a second resistive state of the plurality of resistive states in the CMO to exhibit switching properties. 22. The re-writeable non-volatile memory device of claim 1 , wherein the second layer of the reactive metal is deposited on the CMO and is less than 200 Å thick. 23. The re-writeable non-volatile memory device of claim 1 , wherein the reactive metal reacts with the CMO to form a layer of reacted metal in the ME such that the ME is a multi-resistive state ME. 24. The re-writeable non-volatile memory device of claim 23 , wherein the reactive metal creates a non-ohmic device within the multi-resistive state ME. 25. The re-writeable non-volatile memory device of claim 1 , wherein the reactive metal is between 10 Å thick and 100 Å thick. 26. The method of claim 10 , wherein the forming the second layer comprises depositing the second layer of the reactive metal on the CMO, wherein the second layer of the reactive metal is less than 200 Å thick. 27. The method of claim 10 , wherein the second layer of the reactive metal is between 10 Å thick and 100 Å thick.

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Classifications

  • Array wherein the access device being a transistor · CPC title

  • Write using potential difference applied between cell electrodes · CPC title

  • using elements in which the storage effect is based on magnetic spin effect · CPC title

  • Material having simple binary metal oxide structure · CPC title

  • Material having complex metal oxide, e.g. perovskite structure · CPC title

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What does patent US9806130B2 cover?
A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of …
Who is the assignee on this patent?
Unity Semiconductor Corp
What technology area does this patent fall under?
Primary CPC classification G11C11/5685. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Oct 31 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).