Local bit lines and methods of selecting the same to access memory elements in cross-point arrays

Patent metadata

Field	Value
Publication number	US-11398256-B2
Application number	US-202016844487-A
Country	US
Kind code	B2
Filing date	Apr 9, 2020
Priority date	Jan 29, 2010
Publication date	Jul 26, 2022
Grant date	Jul 26, 2022

Abstract

Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.

First claim

What is claimed is:

1. A memory device comprising:
a memory array comprising a plurality of word lines, a plurality of bit lines, and a plurality of bit line portions, wherein a plurality of memory elements are positioned at intersections of the plurality of word lines and the plurality of bit line portions; and
a logic layer disposed at least partially under the memory array, the logic layer comprising one or more bit line decoders each to control a group of the plurality of bit line portions to perform a memory operation, wherein when the memory operation comprises a byte erase operation, the group comprises a number of bit line portions associated with one of the plurality of bit lines and intersecting one of the plurality of word lines, and when the memory operation comprises a page erase operation, the group comprises one respective bit line portion associated with each of the plurality of bit lines and intersecting the one of the plurality of word lines.

2. The memory device of claim 1 , wherein each of the one or more bit line decoders is to decode a received memory address and select a corresponding group of the plurality of bit line portions based on the received memory address to perform the memory operation.

3. The memory device of claim 2 , wherein each of the one or more bit line decoders is to access one or more memory elements in a subset of the plurality of memory elements corresponding to at least one bit line portion in the corresponding group of the plurality of bit line portions.

4. The memory device of claim 2 , wherein each of the one or more bit line decoders is to activate a bit line gate to couple at least one bit line portion of the corresponding group of the plurality of bit line portions to a corresponding one of the plurality of bit lines and to decouple one or more other bit line portions of the corresponding group of the plurality of bit line portions from the corresponding one of the plurality of bit lines.

5. The memory device of claim 1 , wherein the memory array comprises a plurality of memory layers.

6. The memory device of claim 1 , wherein the logic layer is disposed at least partially in a periphery of the memory array.

7. An apparatus comprising:
a substrate;
a memory array formed above the substrate, the memory array comprising a plurality of word lines, a plurality of bit lines, and a plurality of bit line portions, wherein a plurality of memory elements are positioned at intersections of the plurality of word lines and the plurality of bit line portions; and
a logic layer formed on the substrate, the logic layer comprising one or more bit line decoders each to control a group of the plurality of bit line portions to perform a memory operation, wherein when the memory operation comprises a byte erase operation, the group comprises a number of bit line portions associated with one of the plurality of bit lines and intersecting one of the plurality of word lines, and when the memory operation comprises a page erase operation, the group comprises one respective bit line portion associated with each of the plurality of bit lines and intersecting the one of the plurality of word lines.

8. The apparatus of claim 7 , wherein each of the one or more bit line decoders is to decode a received memory address and select a corresponding group of the plurality of bit line portions based on the received memory address to perform the memory operation.

9. The apparatus of claim 8 , wherein each of the one or more bit line decoders is to access one or more memory elements in a subset of the plurality of memory elements corresponding to at least one bit line portion in the corresponding group of the plurality of bit line portions.

10. The apparatus of claim 8 , wherein each of the one or more bit line decoders is to activate a bit line gate to couple at least one bit line portion of the corresponding group of the plurality of bit line portions to a corresponding one of the plurality of bit lines and to decouple one or more other bit line portions of the corresponding group of the plurality of bit line portions from the corresponding one of the plurality of bit lines.

11. The apparatus of claim 7 , wherein the memory array comprises a plurality of memory layers.

12. The apparatus of claim 7 , wherein the logic layer is disposed at least partially in a periphery of the memory array.

13. An integrated circuit comprising:
a logic layer formed on a substrate, the logic layer comprising one or more bit line decoders;
a memory comprising one or more layers formed above the substrate, the memory comprising an array comprising a plurality of word lines, a plurality of bit lines, and a plurality of bit line portions, wherein a plurality of memory elements are positioned at intersections of the plurality of word lines and the plurality of bit line portions,
wherein the one or more bit line decoders are each to control a group of the plurality of bit line portions to perform a memory operation, wherein when the memory operation comprises a byte erase operation, the group comprises a number of bit line portions associated with one of the plurality of bit lines and intersecting one of the plurality of word lines, and when the memory operation comprises a page erase operation, the group comprises one respective bit line portion associated with each of the plurality of bit lines and intersecting the one of the plurality of word lines.

14. The integrated circuit of claim 13 , wherein each of the one or more bit line decoders is to decode a received memory address and select a corresponding group of the plurality of bit line portions based on the received memory address to perform the memory operation.

Assignees

• Unity Semiconductor Corp

Inventors

• Siau Chang Hua
• Chevallier Christophe
• Rinerson Darrell
• Lim Seow Fong
• Namala Sri Rama

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C5/025 Primary

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C13/0097

  Erasing, e.g. resetting, circuits or methods · CPC title