Two-terminal reversibly switchable memory device

Patent metadata

Field	Value
Publication number	US-10680171-B2
Application number	US-201916262841-A
Country	US
Kind code	B2
Filing date	Jan 30, 2019
Priority date	Feb 6, 2004
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.

First claim

The invention claimed is:

1. A two-terminal memory cell comprising:
a mixed valence oxide;
a mixed electronic ionic conductor coupled with the mixed valence oxide;
a first memory electrode in contact with the mixed valence oxide; and
a second memory electrode coupled with the mixed electronic ionic conductor.

2. The two-terminal memory cell of claim 1 , wherein:
the mixed electronic ionic conductor is uniform in conduction.

3. The two-terminal memory cell of claim 1 , wherein:
the mixed electronic ionic conductor is lacking in uniformity in conduction.

4. The two-terminal memory cell of claim 3 , wherein:
the uniformity of the mixed electronic ionic conductor varies in a direction from the mixed valence oxide to the second memory electrode.

5. The two-terminal memory cell of claim 3 , wherein:
the uniformity of the mixed electronic ionic conductor varies in a direction orthogonal to a direction from the mixed valence oxide to the second memory electrode.

6. The two-terminal memory cell of claim 1 , wherein:
the mixed valence oxide is uniform in oxidation.

7. The two-terminal memory cell of claim 1 , wherein:
the mixed valence oxide is lacking in uniformity in oxidation.

8. The two-terminal memory cell of claim 7 , wherein:
the uniformity of the mixed valence oxide varies in a direction from the mixed electronic ionic conductor to the first memory electrode.

9. The two-terminal memory cell of claim 8 , wherein:
the uniformity of the mixed valence oxide varies in a direction orthogonal to a direction from the mixed electronic ionic conductor to the first memory electrode.

10. The two-terminal memory cell of claim 1 , wherein the mixed valence oxide is crystalline.

11. A three-terminal memory cell comprising:
a memory element comprising:
a mixed valence oxide, and
a mixed electronic ionic conductor coupled with the mixed valence oxide;

a gate memory electrode coupled with the mixed valence oxide;
a source memory electrode coupled with the memory element; and
a drain memory electrode coupled with the memory element.

12. The three-terminal memory cell of claim 11 , wherein:
the mixed electronic ionic conductor is uniform in conduction.

13. The three-terminal memory cell of claim 11 , wherein:
the mixed electronic ionic conductor is lacking in uniformity in conduction.

14. The three-terminal memory cell of claim 13 , wherein:
the uniformity of the mixed electronic ionic conductor varies in a direction from the mixed valence oxide to at least one of the source memory electrode and the drain memory electrode.

15. The three-terminal memory cell of claim 13 , wherein:
the uniformity of the mixed electronic ionic conductor varies in a direction orthogonal to a direction from the mixed valence oxide to at least one of the source memory electrode and the drain memory electrode.

16. The three-terminal memory cell of claim 11 , wherein:
the mixed valence oxide is uniform in oxidation.

17. The three-terminal memory cell of claim 11 , wherein:
the mixed valence oxide is lacking in uniformity in oxidation.

18. The three-terminal memory cell of claim 17 , wherein:
the uniformity of the mixed valence oxide varies in a direction from the mixed electronic ionic conductor to the gate memory electrode.

19. The three-terminal memory cell of claim 17 , wherein:
the uniformity of the mixed valence oxide varies in a direction orthogonal to a direction from the mixed electronic ionic conductor to the gate memory electrode.

20. The three-terminal memory cell of claim 11 , wherein the mixed valence oxide is crystalline.

Assignees

• Hefei Reliance Memory Ltd

Inventors

• Rinerson Darrell
• Chevallier Christophe J
• Kinney Wayne
• Lambertson Roy
• Sanchez Jr John E
• Schloss Lawrence
• Swab Philip
• Ward Edmond

Classifications

• H01L27/2481

  Electricity · mapped topic

• G11C2213/53

  Structure wherein the resistive material being in a transistor, e.g. gate · CPC title

• G11C2213/54

  Structure including a tunneling barrier layer, the memory effect implying the modification of tunnel barrier conductivity · CPC title

• G11C2013/0045

  Read using current through the cell · CPC title

• G11C2213/31

  Material having complex metal oxide, e.g. perovskite structure · CPC title