Local bit lines and methods of selecting the same to access memory elements in cross-point arrays

Patent metadata

Field	Value
Publication number	US-10002646-B2
Application number	US-201414526894-A
Country	US
Kind code	B2
Filing date	Oct 29, 2014
Priority date	Mar 30, 2005
Publication date	Jun 19, 2018
Grant date	Jun 19, 2018

Abstract

Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.

First claim

What is claimed is:

1. A method comprising:
identifying a region on a substrate;
forming, in the region on the substrate, local bit line decoders, control lines, and switching structures;
forming a cross-point memory array over the region, the cross-point memory array comprising:
X-lines;
Y-lines, wherein the X-lines and the Y-lines are disposed substantially parallel to the substrate;
groups of Y-line portions disposed substantially perpendicular to the substrate, each Y-line portion within a group arranged electrically in parallel with the other Y-line portions in the same group, and each group comprising a plurality of Y-line portions coupled via a respective switching structure to a corresponding one of the Y-lines; and
memory elements formed electrically between a subset of the X-lines and a group of the Y-line portions;

coupling at least one of the local bit line decoders to the switching structures, the at least one of the local bit line decoders being disposed on the substrate below the cross-point memory array and configured to decode a received address to select a corresponding Y-line portion via one of the control lines; and
applying a select voltage signal having a negative voltage to at least one of the Y-lines during a program operation of at least one of the memory elements associated with the at least one of the Y-lines.

2. The method of claim 1 wherein the at least one local bit line decoder drives the corresponding control lines to operate the switching structures to couple the selected Y-line portion to the corresponding Y-line to access a sub-array of the memory elements.

3. The method of claim 2 wherein each of the memory elements has exactly two terminals and a programmable resistivity to store a state as a value of resistance.

4. The method of claim 1 wherein each of the memory elements has exactly two terminals and a programmable resistivity to store a state as a value of resistance.

5. The method of claim 4 , further comprising:
forming the memory elements in a first memory layer overlying the substrate;
forming a second set of memory elements in a second memory layer substantially parallel to the first memory layer; and
arranging at least one of Y-line portions extending through at least the first and second memory layers.

6. The method of claim 1 wherein the switching structures comprise pass gates.

7. The method of claim 6 wherein at least one Y-line pass gate is disposed in a logic layer between the substrate and a bottommost memory layer.

8. A method comprising:
identifying a region on a substrate;
forming, in the region, local bit line decoders, control lines, and switching structures;
forming a cross-point memory array over the region, the cross-point memory array comprising:
X-lines;
Y-lines, wherein the X-lines and the Y-lines are disposed substantially parallel to the substrate;
groups of Y-line portions disposed substantially perpendicular to the substrate, each Y-line portion within a group arranged electrically in parallel with the other Y-line portions in the same group, and each group comprising a plurality of Y-line portions coupled via a respective switching structure to a corresponding one of the Y-lines; and
memory elements formed electrically between a subset of the X-lines and a group of the Y-line portions;

coupling at least one of the local bit line decoders to the switching structures, the at least one of the local bit line decoders being disposed on the substrate below the cross-point memory array;
configuring the local bit line decoders to activate a selected one at a time of the switching structures to couple the corresponding Y-line portion of the memory to the Y-line, and concurrently deactivate the other Y-line switching structures to electrically decouple the other Y-line portions from the one Y-line to access a subset of the memory corresponding to the selected Y-line portion; and
applying a select voltage signal having a negative voltage to at least one of the Y-lines during a program operation of at least one of the memory elements associated with the at least one of the Y-lines.

9. The method of claim 8 wherein each of the memory elements has exactly two terminals and a programmable resistivity to store a state as a value of resistance.

10. The method of claim 9 further comprising:
forming the memory elements in a first memory layer overlying the substrate;
forming a second set of memory elements in a second memory layer substantially parallel to the first memory layer; and
arranging at least one of Y-line portions extending through at least the first and second memory layers.

11. The method of claim 10 wherein the switching structures comprise pass gates.

12. The method of claim 11 wherein the pass gates comprise MOS transistors.

13. The method of claim 10 , further comprising:
configuring the local bit line decoders to decode at least a portion of an address to access one or more memory elements in the subset of the memory, wherein at least a portion of the local bit line decoder is disposed under the subset of the X-lines.

14. The method of claim 10 , further comprising:
forming the local bit line decoder substantially directly under and positioned within a periphery of the memory array.

15. The method of claim 10 , further comprising:
arranging a plurality of local bit line decoders to access one or more memory elements along an X-line substantially simultaneously.

16. The method of claim 15 wherein the plurality of local bit line decoders is to simultaneously access the one or more memory elements along the X-line to perform a write operation.

17. The method of claim 15 wherein the plurality of local bit line decoders is to substantially simultaneously access all of the memory elements along the X-line to perform a page erase operation.

18. The method of claim 12 , further comprising:
scaling the Y-line MOS transistors that are electrically coupled with the one Y-line and the group of Y-line portions, so that the scaled Y-line MOS gates have scaled dimensions commensurate with dimensions of the memory elements that constitute a reduced array size for the memory array, wherein the scaled Y-line MOS gates are disposed directly under and positioned within a periphery of the reduced array size.

19. A method comprising:
identifying a region on a substrate;
forming, in the region on the substrate, local bit line decoders, control lines, and switching structures;
forming a cross-point memory array over the region, the cross-point memory array comprising:
X-lines;
Y-lines, wherein the X-lines and the Y-lines are disposed parallel to the substrate;
groups of Y-line portions disposed perpendicular to the substrate, each Y-line portion within a group arranged electrically in parallel with the other Y-line portions in the same group, and each group comprising a plurality of Y-line portions coupled via a respective switching structure to a corresponding one of the Y-lines; and
memory elements formed electrically between a subset of the X-lines and a group of the Y-line portions;

coupling at least one of the local bit line decoders to the switching structures, the at least one of the local bit line decoders being disposed on the substrate below the cross-point memory array and configured to decode a received address to select a corresponding Y-line portion via one of the control lines; and
applying a select voltage signal having a negative voltage to at least one of the Y-lines during a program operation of at least one

Assignees

• Unity Semiconductor Corp

Inventors

• Siau Chang Hua
• Chevallier Christophe
• Rinerson Darrell
• Lim Seow Fong
• Namala Sri Rama

Classifications

• G11C5/025 Primary

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• H01L27/2481

  Electricity · mapped topic

• G11C2213/77

  Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G11C13/0026

  Bit-line or column circuits · CPC title