Adjusting pulse width based on address signal in memory devices
US-12586628-B2 · Mar 24, 2026 · US
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Nien Yi-Hsin patents
Nien Yi-Hsin is listed as an inventor on 63 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Nien Yi-Hsin |
| Total patents | 63 |
| First publication | May 27, 2021 |
| Latest publication | Mar 24, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Memory devices and methods of manufacturing thereof
US-2026082531-A1 · Mar 19, 2026 · US
Systems and methods to mitigate cycle time degradation by nbti effect on pdp sram
US-2026031141-A1 · Jan 29, 2026 · US
Latch circuits and methods for operating the same
US-12531549-B2 · Jan 20, 2026 · US
Memory devices and methods for manufacturing the same
US-2025374505-A1 · Dec 4, 2025 · US
Memory device and method of operating the same
US-2025364038-A1 · Nov 27, 2025 · US
Devices and methods for adjusting signal pulse width
US-2025356906-A1 · Nov 20, 2025 · US
Semiconductor memory devices with flying bit lines and methods of manufacturing thereof
US-2025349326-A1 · Nov 13, 2025 · US
Memory device and method of operating the same
US-2025351322-A1 · Nov 13, 2025 · US
Latch circuits and methods for operating the same
US-2025343537-A1 · Nov 6, 2025 · US
Recent patents
Latest publications not already listed above.
Memory devices with via structrues and methods of manufacturing thereof
US-2025343132-A1 · Nov 6, 2025 · US
Memory device
US-2025318098-A1 · Oct 9, 2025 · US
Memory device including separate negative bit line
US-12387768-B2 · Aug 12, 2025 · US
Memory device
US-12369292-B2 · Jul 22, 2025 · US
Memory device having a negative voltage circuit
US-12367929-B2 · Jul 22, 2025 · US
Memory device and method of operating the same
US-2025220868-A1 · Jul 3, 2025 · US
Memory devices with improved bit line loading
US-2025201303-A1 · Jun 19, 2025 · US
Bitcell supporting bit-write-mask function
US-12334145-B2 · Jun 17, 2025 · US
Memory device including a word line with portions with different sizes in different metal layers
US-2025157531-A1 · May 15, 2025 · US
Memory devices configured with pulse adjustment and methods for operating the same
US-2025124966-A1 · Apr 17, 2025 · US
Memory devices with switchable power delivery paths
US-2025118632-A1 · Apr 10, 2025 · US
Memory devices with improved bit line loading
US-12260903-B2 · Mar 25, 2025 · US
Systems and Methods for Memory Operation Using Local Word Lines
US-2025078889-A1 · Mar 6, 2025 · US
Memory cell with buried power grid, and method of fabricating same
US-2025063709-A1 · Feb 20, 2025 · US
Memory device including a word line with portions with different sizes in different metal layers
US-12230318-B2 · Feb 18, 2025 · US
Semiconductor memory devices with flying bit lines and methods of manufacturing thereof
US-2025014614-A1 · Jan 9, 2025 · US
Latch circuits and methods for operating the same
US-2024429902-A1 · Dec 26, 2024 · US
Fly shared bit line on 4-cpp static random access memory (sram) cell and array
US-2024404588-A1 · Dec 5, 2024 · US
Systems and methods for memory operation using local word lines
US-12159688-B2 · Dec 3, 2024 · US
Memory device and method of manufacturing the same
US-2024386945-A1 · Nov 21, 2024 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Taiwan Semiconductor Mfg Co Ltd | 64 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C11/419 | 42 |
| H10B10/12 | 40 |
| G11C11/412 | 36 |
| H10D89/10 | 25 |
| G11C11/418 | 17 |