Systems and methods to mitigate cycle time degradation by nbti effect on pdp sram

Patent metadata

Field	Value
Publication number	US-2026031141-A1
Application number	US-202418786316-A
Country	US
Kind code	A1
Filing date	Jul 26, 2024
Priority date	Jul 26, 2024
Publication date	Jan 29, 2026
Grant date	—

Abstract

A memory circuit includes a memory array comprising a plurality of memory cells. The memory circuit includes a first pre-charge circuit coupled to at least one access line electrically connected to the plurality of memory cells and configured to be in a first state during a standby mode of the memory array. The memory circuit includes a second pre-charge circuit coupled to the at least one access line and configured to be in a second state during the standby mode.

First claim

What is claimed is:

1 . A memory circuit, comprising:
a memory array comprising a plurality of memory cells; a first pre-charge circuit coupled to at least one access line electrically connected to the plurality of memory cells, and configured to be in a first state during a standby mode of the memory array; and a second pre-charge circuit coupled to the at least one access line, and configured to be in a second state during the standby mode.

2 . The memory circuit of claim 1 , wherein the second state is indicative of an inactive pre-charge circuit to suspend charging the at least one access line and the first state is indicative of an active pre-charge circuit to charge the at least one access line to a supply voltage, and wherein in the first state during the standby mode, the first pre-charge circuit is configured to charge the at least one access line to the supply voltage prior to accessing the plurality of memory cells.

3 . The memory circuit of claim 1 , wherein the standby mode is associated with a time period when an access operation is suspended.

4 . The memory circuit of claim 1 , wherein:
the first pre-charge circuit is configured to be in the second state to suspend charging the at least one access line during a read operation and a write operation of the plurality of memory cells; and the second pre-charge circuit remains in the second state during the read operation and the write operation.

5 . The memory circuit of claim 4 , wherein the read operation and the write operation of the plurality of memory cells correspond to an access operation performed in one clock cycle

6 . The memory circuit of claim 4 , wherein the first pre-charge circuit and the second pre-charge circuit are in the first state during a predefined time period between the read operation and the write operation to charge the at least one access line.

7 . The memory circuit of claim 1 , further comprising:
at least one word line coupled to the plurality of memory cells, and configured to be charged to a supply voltage during a read operation or a write operation of the plurality of memory cells for respective predefined first time periods, wherein the first pre-charge circuit is in the second state to suspend charging the at least one access line during the read operation and the write operation for predefined second time periods associated with the respective predefined first time periods.

8 . The memory circuit of claim 7 , wherein the at least one access line discharges during the read operation of the plurality of memory cells, wherein the at least one access line recharges after the read operation, when the first pre-charge circuit and the second pre-charge circuit are in the first state, and wherein a time period of recharging the at least one access line is predetermined.

9 . The memory circuit of claim 8 , wherein the at least one word line is charged to the supply voltage for the write operation at a time instance when the first pre-charge circuit and the second pre-charge circuit are in the second state.

10 . The memory circuit of claim 1 , wherein one or more of the plurality of memory cells correspond to a pseudo-dual-port (PDP) static random access memory (SRAM), wherein the PDP SRAM is configured to performing a read operation and a write operation within one clock cycle.

11 . The memory circuit of claim 1 , wherein:
the at least one access line comprises a first access line and a second access line; the first pre-charge circuit comprises:
a first transistor operatively coupled to the first access line,
a second transistor operatively coupled to the second access line, and
a third transistor operatively coupled to the first access line and the second access line, and configured to equalize charges of the first access line and the second access line, wherein respective gates of the first, second, and third transistors are operatively coupled; and
the second pre-charge circuit comprises:
a fourth transistor operatively coupled to the first access line,
a fifth transistor operatively coupled to the second access line, and
a sixth transistor operatively coupled to the first access line and the second access line, and configured to equalize charges of the first access line and the second access line, wherein respective gates of the fourth, fifth, and sixth transistors are operatively coupled.

12 . A memory circuit, comprising:
a memory array comprising a plurality of memory cells; a pre-charge circuit coupled to a first access line and a second access line electrically connected to the plurality of memory cells, and configured to be in a low state during a standby mode of the memory array; and an equalizer circuit coupled to the first access line and the second access line, and configured to be in a high state during the standby mode.

13 . The memory circuit of claim 12 , wherein the high state is indicative of an inactive pre-charge circuit to suspend charging the first access line and the second access line or an inactive equalizer circuit to suspend equalizing charges of the first access line and the second access line, and the low state is indicative of an active pre-charge circuit to charge the first access line and the second access line to a supply voltage or an active equalizer circuit to equalize charges of the first access line and the second access line, and wherein in the low state during the standby mode, the pre-charge circuit is configured to charge the first access line and the second access line to the supply voltage prior to accessing the plurality of memory cells.

14 . The memory circuit of claim 12 , wherein:
the pre-charge circuit is configured to be in the high state to suspend charging at least one of the first access line or the second access line during a read operation and a write operation of the plurality of memory cells; the equalizer circuit remains in the high state during the read operation and the write operation to suspend equalizing a first charge of the first access line to a second charge of the second access line; and the pre-charge circuit and the equalizer circuit are in the low state between the read operation and the write operation, wherein in the low state, the pre-charge circuit is configured to charge the first access line and the second access line to a supply voltage and the equalizer circuit is configured to equalize the first charge of the first access line to the second charge of the second access line.

15 . The memory circuit of claim 14 , wherein the read operation and the write operation of the plurality of memory cells are performed in one clock cycle.

16 . The memory circuit of claim 14 , wherein a respective time period of at least one of the read operation, the write operation, the high state of the pre-charge circuit, the low state of the pre-charge circuit and the equalizer circuit between the read operation and the write operation, or between the read operation and the write operation is predefined.

17 . The memory circuit of claim 12 , wherein:
the pre-charge circuit comprises:
a first transistor operatively coupled to the first access line,
a second transistor operatively coupled to the second access line, and
a third transistor operatively coupled to the first access line and the second access line, and configured to equalize the first access line and the second access line, wherein respective gates of the first, second, and third transistors are operatively coupled; and
the equalizer circuit comprises:
a fourth transistor operatively coupled to the first a

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Nien Yi-Hsin
• Lin Chih-Yu
• Fujiwara Hidehiro
• Chen Yen-Huei

Classifications

• H10B10/12

  comprising a MOSFET load element · CPC title

• G11C11/412 Primary

  using field-effect transistors only · CPC title

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/30 Primary

  Power supply circuits · CPC title