Devices and methods for adjusting signal pulse width

Patent metadata

Field	Value
Publication number	US-2025356906-A1
Application number	US-202519280802-A
Country	US
Kind code	A1
Filing date	Jul 25, 2025
Priority date	Oct 13, 2023
Publication date	Nov 20, 2025
Grant date	—

Abstract

A memory device includes a memory array including a plurality of word lines, each of the plurality of word lines operatively coupled to a corresponding set of memory cells, and a controller operatively coupled to the memory array. The controller is configured to receive a first address signal indicating a first word line that is physically arranged with respect to the controller by a first distance, assert the first word line through a first signal with a first pulse width, receive a second address signal indicating a second word line that is physically arranged with respect to the controller by a second distance, assert the second word line through a second signal with a second pulse width, and adjust one of the first pulse width or the second pulse width based on the first distance and the second distance.

First claim

What is claimed is:

1 . A memory device, comprising:
a memory array comprising a plurality of word lines, each of the plurality of word lines operatively coupled to a corresponding set of memory cells; and a controller operatively coupled to the memory array, wherein the controller is configured to:
receive an address signal indicating a word line, among the plurality of word lines, located at a distance from the controller;
generate a word line signal for asserting the word line;
determine, based at least in part on the address signal, a physical location of the word line with respect to the controller; and
adjust a pulse width of the word line signal to be conducted through the word line based on the physical location of the word line relative to the controller.

2 . The memory device of claim 1 , wherein the controller is configured to adjust the pulse width, in response to identifying that the word line is located physically closer to the controller than another word line is.

3 . The memory device of claim 1 , wherein the controller is configured to adjust the pulse width to be proportional to the physical location of the word line.

4 . The memory device of claim 1 , wherein the controller is configured to adjust the pulse width by adjusting a pulse width of a clock pulse associated with the word line.

5 . The memory device of claim 1 , further comprising:
a plurality of tracking cells corresponding to the plurality of word lines, respectively, wherein the plurality of tracking cells are physically located corresponding to the plurality of word lines, respectively.

6 . The memory device of claim 5 , wherein the controller is configured to:
assert a tracking cell, among the plurality of tracking cells and corresponding to the word line, through a tracking signal according to the address signal; and adjust a pulse width of the tracking signal based on the address signal.

7 . The memory device of claim 6 , wherein a slope of the tracking signal corresponds to a physical location of the tracking cell.

8 . The memory device of claim 1 , further comprising:
a plurality of logic delay circuits corresponding to the plurality of word lines, respectively, each logic delay circuit configured to provide a corresponding reset signal.

9 . The memory device of claim 8 , wherein the controller is configured to adjust, according to the distance, a width of the reset signal corresponding to the word line.

10 . A memory device, comprising:
a memory array comprising a plurality of word lines, each of the plurality of word lines operatively coupled to a corresponding set of memory cells; and a controller operatively coupled to the memory array, wherein the controller is configured to:
assert a word line through a signal according to an address signal;
based at least in part on the address signal, identify a physical location of the word line; and
in response to a determination that the word line is within a predetermined distance from the controller, adjust a pulse width of the signal.

11 . The memory device of claim 10 , wherein the controller is configured to reduce the pulse width of the signal, in response to identifying that the word line is located physically closer to the controller than another word line is.

12 . The memory device of claim 10 , wherein the controller is configured to adjust the pulse width of the signal by adjusting a pulse width of a clock pulse associated with the signal.

13 . The memory device of claim 10 , further comprising:
a tracking cell corresponding to the word line; wherein the tracking cell is physically located corresponding to the word line.

14 . The memory device of claim 13 , wherein the controller is configured to:
assert the tracking cell through a tracking signal according to the address signal; and adjust a pulse width of the tracking signal based on the physical location.

15 . The memory device of claim 14 , wherein a slope of the tracking signal corresponds to a physical location of the tracking cell.

16 . The memory device of claim 10 , further comprising:
a plurality of logic delay circuits corresponding to the plurality of word lines, respectively, each logic delay circuit configured to provide a corresponding reset signal.

17 . The memory device of claim 16 , wherein the controller is configured to adjust, according to the physical location, a width of the reset signal corresponding to the word line.

18 . A method for operating memory devices, comprising:
receiving, by a controller, an address signal indicating one of a plurality of word lines of a memory array; asserting, by the controller, the word line through a signal with a pulse width; and adjusting, by the controller, the pulse width in response to identifying a physical location of the word line.

19 . The method of claim 18 , further comprising:
adjusting, by the controller, a pulse width of a tracking signal corresponding to the word line, in response to identifying the physical location of the word line.

20 . The method of claim 18 , further comprising:
adjusting, by the controller, a pulse width of a reset signal corresponding to the word line, in response to identifying the physical location of the word line.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Fujiwara Hidehiro
• Nien Yi-Hsin
• Reddy Konudula Venkateswara
• Puri Nikhil
• Chen Yen-Huei

Classifications

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C11/412

  using field-effect transistors only · CPC title

• G11C11/413 Primary

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction · CPC title

• G11C11/418

  Address circuits · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title