Systems and methods for memory operation using local word lines

Patent metadata

Field	Value
Publication number	US-12159688-B2
Application number	US-202318328842-A
Country	US
Kind code	B2
Filing date	Jun 5, 2023
Priority date	Jan 16, 2020
Publication date	Dec 3, 2024
Grant date	Dec 3, 2024

Abstract

Systems and method are provided for a memory circuit. In embodiments, the circuit includes a plurality of memory cells corresponding to a word of data and a global write word line. A plurality of local write lines are connected to a subset of the plurality of memory cells of the word of data. Selection logic is configured to activate a particular subset of memory cells for writing via a particular local write line based on a signal on the global write word line and a selection signal associated with the particular subset of memory cells.

First claim

What is claimed is:

1. A method comprising:
receiving a selection signal on one of a plurality of selection lines, each selection line being associated with a subset of a plurality of memory cells;
operating a selection logic to generate a signal on a local write line connected to the subset of the plurality of memory cells; and
writing data to the subset of the plurality of memory cells.

2. The method of claim 1 , further comprising providing a signal on a write word line that is provided to memory cells that correspond to a word of data.

3. The method of claim 1 , wherein the selection logic is configured to generate the signal on the local write line and a signal on a local write line bar.

4. The method of claim 3 , wherein the signals on the local write line and the local write line bar are generated using a single NAND gate and a single inverter or a single NOR gate and a single inverter.

5. A signal network comprising:
a selection signal line associated with a subset of a plurality of memory cells; and
a local write line connected to the subset of the plurality of memory cells, wherein the local write line is further connected to a selection logic configured to receive a signal from the selection signal line.

6. The signal network of claim 5 , wherein a gate of a pull down transistor controlled using a signal on a read word line is connected to a storage node of a particular memory cell.

7. The signal network of claim 5 , wherein a global write word line is not directly connected to any of the plurality of memory cells.

8. The signal network of claim 5 , wherein a particular memory cell is responsive to a write input and a write bar input and a selection logic is configured to generate signals to the write input and the write bar input.

9. The signal network of claim 5 , wherein a particular memory cell is configured to store data from a data input of the particular memory cell when the particular memory cell is a member of a particular subset of memory cells activated by a selection logic.

10. The signal network of claim 5 , wherein a particular memory cell is responsive to a read input, a write input, a write bar input.

11. The signal network of claim 10 , wherein a selection logic is configured to generate signals for the write input and the write bar input using one NAND gate and one inverter.

12. The signal network of claim 10 , wherein a selection logic is configured to generate signals for the write input and the write bar input using one NOR gate and one inverter.

13. The signal network of claim 5 , wherein a word of data correspond to M bits and the local write line is configured to control M/N bits.

14. The signal network of claim 13 , wherein M=64; N=8; and M/N=8.

15. The signal network of claim 13 , wherein the signal network is configured to operate a memory circuit that includes M/N pins for inputting data to write.

16. The signal network of claim 13 , wherein the signal network is configured to operate a memory circuit that includes M or M/N pins for outputting read data.

17. The signal network of claim 13 , wherein the signal network is configured to operate a memory circuit that is configured for simultaneous writing of x*M/N bits at a time, where x is an integer between 1 and N.

18. The signal network of claim 5 , wherein the memory cells are 2P8T, 2P10T, or 3P10T memory cells.

19. A method comprising:
receiving a selection signal;
transmitting a signal on a local write line connected to a plurality of memory cells based on the selection signal; and
writing data to the plurality of memory cells.

20. The method of claim 19 , further comprising providing a signal on a write word line that is provided to memory cells that correspond to a word of data.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Nien Yi-Hsin
• Fujiwara Hidehiro
• Chen Yen-Huei

Classifications

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title

• G11C8/08 Primary

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title