Memory device and method of operating the same

Patent metadata

Field	Value
Publication number	US-2025351322-A1
Application number	US-202519280836-A
Country	US
Kind code	A1
Filing date	Jul 25, 2025
Priority date	Jan 3, 2024
Publication date	Nov 13, 2025
Grant date	—

Abstract

An integrated circuit chip includes a first and second memory cell array, and a first and second bit line. The first memory cell array has a first width and a first height. Each memory cell in the first memory cell array includes a first number of transistors. The second memory cell array has a second width and a second height. Each memory cell in the second memory cell array includes the first number of transistors. The first bit line overlaps and is coupled to the first memory cell array, and is on a first metal layer above a front-side of a substrate. The second bit line overlaps and is coupled to the second memory cell array, and is on the first metal layer. At least the first width is different from the second width, or the first height is different from the second height.

First claim

What is claimed is:

1 . An integrated circuit chip, comprising:
a first memory cell array having a first width in a first direction and a first height in a second direction different from the first direction, each memory cell in the first memory cell array includes a first number of transistors; a second memory cell array having a second width in the first direction and a second height in the second direction, each memory cell in the second memory cell array includes the first number of transistors; a first bit line extending in the first direction, being coupled to the first memory cell array, overlapping the first memory cell array, and being on a first metal layer, the first metal layer being above a front-side of a substrate; and a second bit line extending in the first direction, being coupled to the second memory cell array, overlapping the second memory cell array, and being on the first metal layer, wherein at least the first width is different from the second width, or the first height is different from the second height.

2 . The integrated circuit chip of claim 1 , further comprising:
a first set of word lines extending in the second direction, being coupled to the first memory cell array, overlapping the first memory cell array, and being on a second metal layer different from the first metal layer; and a second set of word lines extending in the second direction, being coupled to the second memory cell array, overlapping the second memory cell array, and being on the second metal layer.

3 . The integrated circuit chip of claim 2 , wherein
the first bit line has a first length in the first direction; the first set of word lines have a second length in the second direction; the second bit line has a third length in the first direction; and the second set of word lines have a fourth length in the second direction.

4 . The integrated circuit chip of claim 3 , wherein at least one of
the first length is less than the second length, or the third length is greater than the fourth length.

5 . The integrated circuit chip of claim 3 , wherein at least one of
the first length is less than the third length, or the second length is greater than the fourth length.

6 . The integrated circuit chip of claim 2 , wherein
the second memory cell array comprises a first set of rows of memory cells extending in the first direction, and a first set of columns of memory cells extending in the second direction; and the second set of word lines comprises:
a first word line of the second set of word lines overlaps each memory cell in a first column of the first set of columns of memory cells; and
a second word line of the second set of word lines overlaps each memory cell in the first column of the first set of columns of memory cells, the second word line is adjacent to the first word line; and
the first word line and the second word line are electrically coupled to interleaved memory cells in the first column of the first set of columns of memory cells.

7 . The integrated circuit chip of claim 6 , wherein the first set of rows of memory cells comprises:
a first row including a first memory cell; a second row including a second memory cell; a third row including a third memory cell; and a fourth row including a fourth memory cell.

8 . The integrated circuit chip of claim 7 , wherein the first set of rows of memory cells is in the first column of the first set of columns of memory cells.

9 . The integrated circuit chip of claim 1 , wherein
each memory cell in the first memory cell array is a six transistor (6T) memory cell; and each memory cell in the second memory cell array is a 6T memory cell.

10 . The integrated circuit chip of claim 8 , wherein
the second bit line is shared with neighboring rows of memory cells in the second memory cell array.

11 . An integrated circuit chip, comprising:
a first memory cell array having a first width in a first direction and a first height in a second direction different from the first direction; a second memory cell array having a second width in the first direction and a second height in the second direction; a third memory cell array having a third width in the first direction and a third height in the second direction; a first bit line extending in the first direction, being coupled to the first memory cell array, overlapping the first memory cell array, and being on a first metal layer, the first metal layer being above a front-side of a substrate; a second bit line extending in the first direction, being coupled to the second memory cell array, overlapping the second memory cell array, and being on the first metal layer; and a third bit line extending in the first direction, being coupled to the third memory cell array, overlapping the third memory cell array, and being on the first metal layer, wherein at least the second width is different from the first width or the third width, or the second height is different from the first height or the third height.

12 . The integrated circuit chip of claim 11 , further comprising:
a first set of word lines extending in the second direction, being coupled to the first memory cell array, overlapping the first memory cell array, and being on a second metal layer different from the first metal layer; a second set of word lines extending in the second direction, being coupled to the second memory cell array, overlapping the second memory cell array, and being on the second metal layer; and a third set of word lines extending in the second direction, being coupled to the third memory cell array, overlapping the third memory cell array, and being on the second metal layer.

13 . The integrated circuit chip of claim 12 , wherein
the first bit line has a first length in the first direction; the first set of word lines have a second length in the second direction; the second bit line has a third length in the first direction; the second set of word lines have a fourth length in the second direction. the third bit line has a fifth length in the first direction; and the third set of word lines have a sixth length in the second direction.

14 . The integrated circuit chip of claim 13 , wherein at least one of
the first length is less than the second length, the third length is greater than the fourth length, or the fifth length is less than the sixth length.

15 . The integrated circuit chip of claim 13 , wherein at least one of
the first length is less than at least one of the third length or the fifth length, or the second length is greater than at least one of the fourth length or the sixth length.

16 . The integrated circuit chip of claim 12 , wherein
the second memory cell array comprises a first set of rows of memory cells extending in the first direction, and a first set of columns of memory cells extending in the second direction; and the second set of word lines comprises:
a first word line of the second set of word lines overlaps each memory cell in a first column of the first set of columns of memory cells; and
a second word line of the second set of word lines overlaps each memory cell in the first column of the first set of columns of memory cells, the second word line is adjacent to the first word line; and
the first word line and the second word line are electrically coupled to interleaved memory cells in the first column of the first set of columns of memory cells.

17 . The integrated circuit chip of claim 16 , wherein the first set of rows of memory cells comprises:
a first row inc

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Nien Yi-Hsin
• Lin Chih-Yu
• Fujiwara Hidehiro
• Chen Yen-Huei

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/031

  of conductive parts of the interconnections · CPC title

• H10W20/435 Primary

  Cross-sectional shapes or dispositions of interconnections · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• H10B10/18

  Peripheral circuit regions · CPC title