Memory device including separate negative bit line

Patent metadata

Field	Value
Publication number	US-12387768-B2
Application number	US-202318170426-A
Country	US
Kind code	B2
Filing date	Feb 16, 2023
Priority date	Sep 26, 2022
Publication date	Aug 12, 2025
Grant date	Aug 12, 2025

Abstract

Disclosed herein are related to a memory device. In one aspect, a memory device includes a set of memory cells. In one aspect, the memory device includes a first bit line extending along a direction. The first bit line may be coupled to a subset of the set of memory cells disposed along the direction. In one aspect, the memory device includes a second bit line extending along the direction. In one aspect, the memory device includes a switch coupled between the first bit line and the second bit line.

First claim

What is claimed is:

1. A device comprising:
a set of memory cells;
a first bit line extending along a direction, the first bit line coupled to a subset of the set of memory cells disposed along the direction, wherein the first bit line is configured to be applied with a positive voltage;
a second bit line extending along the direction, wherein the second bit line is configured to be applied with a negative voltage; and
a switch coupled between the first bit line and the second bit line, wherein the switch is configured to selectively connect the second bit line to the first bit line for applying the negative voltage during the write operation while maintaining positive voltage on an unselected subset of memory cells coupled to the first bit line.

2. The device of claim 1 , wherein the second bit line has a lower resistance than the first bit line.

3. The device of claim 1 ,
wherein the first bit line is disposed in a first layer, and
wherein the second bit line is disposed in a second layer.

4. The device of claim 3 , wherein the set of memory cells is disposed in a third layer.

5. The device of claim 4 , wherein the third layer is between the first layer and the second layer.

6. The device of claim 4 , wherein the first layer is between the second layer and the third layer.

7. The device of claim 1 , further comprising:
a driver circuit to:
apply, during a first time period, a first voltage to a memory cell of the set of memory cells through the first bit line to write data at the memory cell, and
apply, during a second time period, a second voltage lower than the first voltage to the memory cell of the set of memory cells through the second bit line, the switch, and the first bit line to write the data to the memory cell.

8. The device of claim 7 ,
wherein the switch is disabled during the first time period, and
wherein the switch is enabled during the second time period.

9. The device of claim 7 ,
wherein the subset of the set of memory cells includes a first memory cell and a second memory cell,
wherein the first memory cell is closer to the switch than the second memory cell, and
wherein the second memory cell is closer to the driver circuit than the first memory cell.

10. The device of claim 7 , further comprising:
another driver circuit to:
apply, during the first time period, the first voltage to the memory cell of the set of memory cells through the first bit line to write the data to the memory cell, and
apply, during the second time period, the second voltage lower than the first voltage to the memory cell of the set of memory cells through the second bit line, the switch, and the first bit line to write the data to the memory cell,

wherein a first portion of the subset of the set of memory cells is disposed between the driver circuit and the switch, and
wherein a second portion of the subset of the set of memory cells is disposed between the another driver circuit and the switch.

11. A device comprising:
a first bit line coupled to a set of memory cells;
a second bit line;
a switch to selectively couple the first bit line and the second bit line; and
a controller configured to:
control the switch to couple the second bit line to the first bit line during a write operation to a selected memory cell of the set of memory cells;
apply a negative voltage from the second bit line to the first bit line during the write operation while the switch is coupled; and
maintain a positive voltage on the first bit line for unselected memory cells of the set of memory cells during the write operation; wherein the second bit line has a two times lower resistance than the first bit line.

12. The device of claim 11 ,
wherein the first bit line is disposed in a first layer, and
wherein the second bit line is disposed in a second layer.

13. The device of claim 12 , wherein the set of memory cells is disposed in a third layer.

14. The device of claim 13 , wherein the third layer is between the first layer and the second layer.

15. The device of claim 13 , wherein the first layer is between the second layer and the third layer.

16. The device of claim 11 , further comprising:
a driver circuit to:
apply, during a first time period, a first voltage to a memory cell of the set of memory cells through the first bit line to write data at the memory cell, and
apply, during a second time period, a second voltage lower than the first voltage to the memory cell of the set of memory cells through the second bit line, the switch, and the first bit line to write the data to the memory cell.

17. The device of claim 16 ,
wherein the switch is disabled during the first time period, and
wherein the switch is enabled during the second time period.

18. A method comprising:
disabling, by a controller, a switch coupled between a first bit line and a second bit line during a first time period, the first bit line coupled to a set of memory cells, wherein the second bit line has a lower resistance than the first bit line;
applying, by the controller, a positive first voltage to a memory cell of the set of memory cells through the first bit line during the first time period to write data to the memory cell;
enabling, by the controller, the switch during a second time period after stopping application of the positive first voltage; and
applying, by the controller, a negative second voltage to the memory cell of the set of memory cells through the second bit line, the switch and the first bit line during the second time period to assist writing the data to the memory cell.

19. The method of claim 18 , wherein the second bit line has a lower resistance than the first bit line.

20. The method of claim 18 ,
wherein the first bit line is disposed in a first layer,
wherein the second bit line is disposed in a second layer,
wherein the set of memory cells is disposed in a third layer, and
wherein the first layer is between the second layer and the third layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Chih-Yu
• Nien Yi-Hsin
• Fujiwara Hidehiro
• Chen Yen-Huei

Classifications

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G11C2207/005

  Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines · CPC title