Latch circuits and methods for operating the same

Patent metadata

Field	Value
Publication number	US-2025343537-A1
Application number	US-202519269489-A
Country	US
Kind code	A1
Filing date	Jul 15, 2025
Priority date	Jun 23, 2023
Publication date	Nov 6, 2025
Grant date	—

Abstract

A circuit includes a first Dual Interlocked Storage Cell (DICE) component, a second DICE component, a third DICE component, and a fourth DICE component operatively coupled to one another as a loop. The first and second DICE components form a first sub-latch configured to receive an input signal, the third and fourth DICE components form a second sub-latch configured to receive the same input signal, the first sub-latch is configured to provide, at a first node, an intermediate signal based on the input signal, and the second sub-latch is configured to provide, at a second node, the same intermediate signal based on the input signal. The circuit includes a first inverter configured to logically invert the intermediate signal and provide, at a third node, an output signal. The circuit includes a second inverter configured to logically invert the intermediate signal and provide, at the third node, the output signal.

First claim

What is claimed is:

1 . A circuit, comprising:
a global input terminal configured to receive an input signal; a global output terminal configured to provide an output signal; a first sub-latch coupled to the global input terminal, and comprising a first Dual Interlocked Storage Cell (DICE) component and a second DICE component; a second sub-latch coupled to the global input terminal, and comprising a third DICE component and a fourth DICE component; a first buffer having a first buffer input coupled to a first transmission gate of the first sub-latch and a second transmission gate of the first sub-latch and a first buffer output coupled to the global output terminal; and a second buffer having a second buffer input coupled to a third transmission gate of the second sub-latch and a fourth transmission gate of the second sub-latch and a second buffer output coupled to the global output terminal; wherein the first DICE component and the third DICE component are configured to be in a first operation state, while the second DICE component and fourth DICE component are configured to be in a second, different operation state.

2 . The circuit of claim 1 , wherein the first buffer input is coupled to an output of the first transmission gate and an input of the second transmission gate, and the second buffer input is coupled to an output of the third transmission gate and an input of the fourth transmission gate.

3 . The circuit of claim 1 , wherein the first transmission gate and the third transmission gate are coupled to the global input terminal.

4 . The circuit of claim 1 , wherein each of the first to fourth DICE components comprises a corresponding p-type transistor and a corresponding n-type transistor.

5 . The circuit of claim 4 , wherein each of the first to fourth DICE components includes a respective first input terminal, a respective second input terminal, and a respective output terminal.

6 . The circuit of claim 5 ,
wherein the respective first input terminal of the first DICE component is a first common node connecting the p-type transistor corresponding to the first DICE component and the n-type transistor corresponding to the third DICE component, the respective second input terminal of the first DICE component is a second common node connecting the n-type transistor corresponding to the first DICE component and the p-type transistor corresponding to the third DICE component, the respective output terminal of the first DICE component is a third common node connecting the p-type transistor corresponding to the second DICE component and the n-type transistor corresponding to the fourth DICE component; wherein the respective first input terminal of the second DICE component is the third common node connecting the p-type transistor corresponding to the second DICE component and the n-type transistor corresponding to the fourth DICE component, the respective second input terminal of the second DICE component is a fourth common node connecting the n-type transistor corresponding to the second DICE component and the p-type transistor corresponding to the fourth DICE component, and the respective output terminal of the second DICE component is coupled to the second transmission gate wherein the respective first input terminal of the third DICE component is the second common node connecting the n-type transistor corresponding to the first DICE component and the p-type transistor corresponding to the third DICE component, the respective second input terminal of the third DICE component is the first common node connecting the n-type transistor corresponding to the first DICE component and the p-type transistor corresponding to the third DICE component, and the respective output terminal of the third DICE component is a fifth common node connecting the n-type transistor of the second DICE component and the p-type transistor corresponding to the fourth DICE component; wherein the respective first input terminal of the fourth DICE component is the fifth common node connecting the n-type transistor corresponding to the second DICE component and the p-type transistor corresponding to the fourth DICE component, the respective second input terminal of the second DICE component is the third common node connecting the p-type transistor corresponding to the second DICE component and the n-type transistor corresponding to the fourth DICE component, and the respective output terminal of the fourth DICE component is coupled to the fourth transmission gate.

7 . The circuit of claim 6 , wherein the first buffer input is coupled to the second common node and the second buffer input is coupled to the first common node.

8 . The circuit of claim 6 , further comprising:
a first p-type transistor coupled to the respective output terminal of the second DICE component and a first n-type transistor coupled to the n-type transistor of the second DICE component; and a second p-type transistor coupled to the respective output terminal of the fourth DICE component and a second n-type transistor coupled to the n-type transistor of the fourth DICE component.

9 . The circuit of claim 7 ,
wherein a drain of the first p-type transistor is coupled to the respective output terminal of the second DICE component and a drain of the second p-type transistor is coupled to the respective output terminal of the fourth DICE component; and wherein a gate of first p-type transistor, a gate of the first n-type transistor, a gate of the second p-type transistor, and a gate of the second n-type transistor are coupled together.

10 . A circuit comprising:
a first Dual Interlocked Storage Cell (DICE) component, a second DICE component, a third DICE component, and a fourth DICE component operatively coupled together to form a loop, wherein the first DICE component and the second DICE component form a first sub-latch configured to receive an input signal, the third DICE component and the fourth DICE component form a second sub-latch configured to receive the input signal, wherein the first sub-latch is configured to provide, at a first node of the first sub-latch, a first intermediate signal based on the input signal and a first transmission gate of the first sub-latch, and the second sub-latch is configured to provide, at a second node of the second sub-latch, a second intermediate signal based on the input signal and a second transmission gate of the second sub-latch; a first inverter coupled to the first transmission gate of the first sub-latch and configured to logically invert the first intermediate signal and provide, at a third node, an output signal; and a second inverter coupled to the second transmission gate of the first sub-latch and configured to logically invert the second intermediate signal and provide, at the third node, the output signal.

11 . The circuit of claim 10 , wherein the first inverter is coupled to an output of the first transmission gate and the second inverter is coupled to an output of the second transmission gate.

12 . The circuit of claim 10 , wherein the first transmission gate and the second transmission gate are coupled to the input signal.

13 . The circuit of claim 10 , wherein each of the first to fourth DICE components comprises a corresponding p-type transistor and a corresponding n-type transistor.

14 . The circuit of claim 13 , wherein each of the first to fourth DICE components includes a respective first input terminal, a respective second input terminal, and a respective output terminal.

15 . The circuit of claim 14 ,
wherein the respective first input terminal of the first DICE comp

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Fujiwara Hidehiro
• Li Yu Jung
• Chiang Yueh
• Zhao Wei-Chang
• Nien Yi-Hsin
• Khare Kinshuk

Classifications

• H03K3/037 Primary

  Bistable circuits · CPC title

• H03K3/356191

  with synchronous operation · CPC title

• H03K3/356156

  with synchronous operation · CPC title

• H03K3/0372

  of the primary-secondary type · CPC title

• H03K3/0375 Primary

  provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00) · CPC title