Adjusting pulse width based on address signal in memory devices

Patent metadata

Field	Value
Publication number	US-12586628-B2
Application number	US-202418402107-A
Country	US
Kind code	B2
Filing date	Jan 2, 2024
Priority date	Oct 13, 2023
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

A memory device includes a memory array including a plurality of word lines, each of the plurality of word lines operatively coupled to a corresponding set of memory cells, and a controller operatively coupled to the memory array. The controller is configured to receive a first address signal indicating a first word line that is physically arranged with respect to the controller by a first distance, assert the first word line through a first signal with a first pulse width, receive a second address signal indicating a second word line that is physically arranged with respect to the controller by a second distance, assert the second word line through a second signal with a second pulse width, and adjust one of the first pulse width or the second pulse width based on the first distance and the second distance.

First claim

What is claimed is:

1 . A memory device, comprising:
a memory array comprising a plurality of word lines, each of the plurality of word lines operatively coupled to a corresponding set of memory cells; and a controller operatively coupled to the memory array, wherein the controller is configured to:
receive a first address signal associated with a first word line that is physically arranged with respect to the controller by a first distance, the first address signal indicating the first distance or a first physical location of the first word line;
assert the first word line through a first signal with a first pulse width;
receive a second address signal associated with a second word line that is physically arranged with respect to the controller by a second distance, the second address signal indicating the second distance or a second physical location of the second word line;
assert the second word line through a second signal with a second pulse width; and
adjust, based on (i) the first address signal indicating the first physical location or first location and (ii) the second address signal indicating the second physical location or second location, one of the first pulse width or the second pulse width.

2 . The memory device of claim 1 , wherein the controller is configured to reduce the first pulse width, in response to identifying that the first word line is located physically closer to the controller than the second word line is.

3 . The memory device of claim 1 , wherein the first pulse width is shorter than the second pulse width, and the first distance is shorter than the second distance.

4 . The memory device of claim 1 , wherein the controller is configured to adjust the one of the first pulse width or the second pulse width by adjusting one of a pulse width of a first clock pulse associated with the first signal or a pulse width of a second clock pulse associated with the second signal.

5 . The memory device of claim 1 , further comprising:
a first tracking cell of a plurality of tracking cells, the first tracking cell corresponding to the first word line; and a second tracking cell of the plurality of tracking cells, the second tracking cell corresponding to the second word line; wherein the first tracking cell and the second tracking cell are physically located corresponding to the first word line and the second word line, respectively.

6 . The memory device of claim 5 , wherein the controller is configured to:
assert the first tracking cell through a first tracking signal according to the first address signal; assert the second tracking cell through a second tracking signal according to the second address signal; and adjust a pulse width of one of the first tracking signal or the second tracking signal based on the first address signal and the second address signal.

7 . The memory device of claim 6 , wherein the first tracking signal has a first slope and the second tracking signal has a second slope, the second slope larger than the first slope.

8 . The memory device of claim 1 , further comprising:
a first logic delay circuit corresponding to the first word line, the first logic delay circuit configured to provide a first reset signal; and a second logic delay circuit corresponding to the second word line, the second logic delay circuit configured to provide a second reset signal; wherein a length of one of the first reset signal or the second reset signal is adjusted according to the first distance and the second distance.

9 . The memory device of claim 8 , wherein the first distance is shorter than the second distance, and a pulse width of the first reset signal is shorter than a pulse width of the second reset signal.

10 . A memory device, comprising:
a memory array comprising a plurality of word lines, each of the plurality of word lines operatively coupled to a corresponding set of memory cells; and a controller operatively coupled to the memory array, wherein the controller is configured to:
assert a first word line through a first signal according to a first address signal indicating a first physical location of the first word line;
assert a second word line through a second signal according to a second address signal indicating a second physical location of the second word line;
based at least in part on the first address signal indicating the first physical location and the second address signal indicating the second physical location, identify a difference in a physical location between the first word line and the second word line; and
in response to a determination that at least one of the first word line or the second word line is within a predetermined distance from the controller, adjust a pulse width of at least one of the first signal or the second signal based on the identified difference in the physical location.

11 . The memory device of claim 10 , wherein the controller is configured to reduce the pulse width of the first signal, based on the identified difference indicating the first word line is located physically closer to the controller than the second word line is.

12 . The memory device of claim 10 , wherein the controller is configured to adjust the pulse width of the at least one of the first signal or the second signal by adjusting one of a pulse width of a first clock pulse associated with the first signal or a pulse width of a second clock pulse associated with the second signal.

13 . The memory device of claim 10 , further comprising:
a first tracking cell of a plurality of tracking cells, the first tracking cell corresponding to the first word line; and a second tracking cell of the plurality of tracking cells, the second tracking cell corresponding to the second word line; wherein the first tracking cell and the second tracking cell are physically located corresponding to the first word line and the second word line, respectively.

14 . The memory device of claim 13 , wherein the controller is configured to:
assert the first tracking cell through a first tracking signal according to the first address signal; assert the second tracking cell through a second tracking signal according to the second address signal; and adjust a pulse width of one of the first tracking signal or the second tracking signal based on the identified difference.

15 . The memory device of claim 14 , wherein the first tracking signal has a first slope and the second tracking signal has a second slope, the second slope larger than the first slope.

16 . The memory device of claim 10 , further comprising:
a first logic delay circuit corresponding to the first word line, the first logic delay circuit configured to provide a first reset signal; and a second logic delay circuit corresponding to the second word line, the second logic delay circuit configured to provide a second reset signal; wherein a pulse width of one of the first reset signal or the second reset signal is adjusted according to the identified difference.

17 . The memory device of claim 16 , wherein a pulse width of the first reset signal is shorter than a pulse width of the second reset signal.

18 . A method for operating memory devices, comprising:
receiving, by a controller, a first address signal associated with a first one of a plurality of word lines of a memory array, the first address signal indicating a first physical location of the first one of the plurality of word lines; asserting, by the controller, the first word line through a first signal with a first pulse width; receiving, b

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Fujiwara Hidehiro
• Nien Yi-Hsin
• Konudula Venkateswara Reddy
• Puri Nikhil
• Chen Yen-Huei

Classifications

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C11/412

  using field-effect transistors only · CPC title

• G11C11/413 Primary

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction · CPC title

• G11C11/418

  Address circuits · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title