Memory devices with via structrues and methods of manufacturing thereof

Patent metadata

Field	Value
Publication number	US-2025343132-A1
Application number	US-202418798980-A
Country	US
Kind code	A1
Filing date	Aug 9, 2024
Priority date	May 3, 2024
Publication date	Nov 6, 2025
Grant date	—

Abstract

A memory device includes a plurality of first memory cells formed in a first area of a substrate, a plurality of first via structures formed in a second area of the substrate, the second area being disposed next to the first area along a first lateral direction, a first one of a plurality of frontside interconnect structures formed on a first side of the substrate, wherein the first frontside interconnect structure is coupled to gate terminals of access transistors of the plurality of first memory cells, and a first one of a plurality of backside interconnect structures formed on a second side of the substrate vertically opposite to the first side, wherein the first backside interconnect structure is coupled to the first frontside interconnect structure through one or more of the plurality of first via structures.

First claim

What is claimed is:

1 . A memory device, comprising:
a plurality of first memory cells formed in a first area of a substrate; a plurality of first via structures formed in a second area of the substrate, the second area being disposed next to the first area along a first lateral direction; a first one of a plurality of frontside interconnect structures formed on a first side of the substrate, wherein the first frontside interconnect structure is coupled to gate terminals of access transistors of the plurality of first memory cells; and a first one of a plurality of backside interconnect structures formed on a second side of the substrate vertically opposite to the first side, wherein the first backside interconnect structure is coupled to the first frontside interconnect structure through one or more of the plurality of first via structures.

2 . The memory device of claim 1 , wherein the first frontside interconnect structure and the first backside interconnect structure both extend along the first lateral direction.

3 . The memory device of claim 1 , further comprising:
a plurality of second memory cells formed in the first area of the substrate; a plurality of second via structures formed in the second area of the substrate; a second one of the plurality of frontside interconnect structures coupled to gate terminals of access transistors of the plurality of second memory cells; and a second one of the plurality of backside interconnect structures coupled to the second frontside interconnect structure through one or more of the plurality of second via structures; wherein the second frontside interconnect structure and the second backside interconnect structure both extend along the first lateral direction.

4 . The memory device of claim 3 , wherein each of the plurality of first memory cells and the plurality of second memory cells includes a static random access memory (SRAM) cell.

5 . The memory device of claim 3 , wherein the second memory cells are aligned with the first memory cells along a second lateral direction perpendicular to the first lateral direction, while the one or more first via structures are displaced from the one or more second via structures in both of the first and second lateral directions.

6 . The memory device of claim 1 , wherein the one or more first via structures each extend through the substrate.

7 . The memory device of claim 6 , further comprising:
a second one of the plurality of frontside interconnect structures, wherein the second frontside interconnect structure is vertically disposed between the substrate and the first frontside interconnect structure; and a second one of the plurality of backside interconnect structures, wherein the second backside interconnect structure is vertically disposed between the substrate and the first backside interconnect structure.

8 . The memory device of claim 7 , wherein the one or more first via structures are each in direct contact with the second frontside interconnect structure and the second backside interconnect structure.

9 . The memory device of claim 7 , wherein the first interconnect structure, the second frontside interconnect structure, and the first backside interconnect structure each extend in the first lateral direction, while the second backside interconnect structure extends in a second lateral direction perpendicular to the first lateral direction.

10 . The memory device of claim 1 , wherein the first frontside interconnect structure and the first backside interconnect structure operatively serve as a portion of a word line of the first memory cells.

11 . The memory device of claim 1 , wherein the first memory cells are configured to be arranged along a row and across a plurality of columns of a memory array, and wherein the memory array is formed in the first area.

12 . A memory device, comprising:
a memory array comprising a plurality of memory cells, wherein the plurality of memory cells are formed in a first area of a substrate; a first interconnect structure formed on a first side of the substrate, wherein the first interconnect structure operatively serves as a first portion of a word line for the plurality of memory cells; a second interconnect structure formed on a second side of the substrate opposite to the first side, wherein the second interconnect structure operatively serves as a second portion of the word line for the plurality of memory cells; and one or more via structures formed in a second area of the substrate next to the first area along a lateral direction, wherein the one or more via structures are configured to couple the first interconnect structure to the second interconnect structure; wherein the first interconnect structure and the second interconnect structure each extend along the lateral direction to traverse both the first and second areas.

13 . The memory device of claim 12 , wherein the one or more via structures each extend through the substrate to connect the first side to the second side of the substrate.

14 . The memory device of claim 12 , wherein the one or more via structures are each formed on the second side of the substrate.

15 . The memory device of claim 14 , further comprising:
at least one transistor formed in the second area of the substrate; wherein a gate terminal and a first source/drain terminal of the at least one transistor is coupled to the first interconnect structure, and a second source/drain terminal of the at least one transistor is coupled to the second interconnect structure through the one or more via structures.

16 . The memory device of claim 12 , wherein each of the plurality of memory cells includes a static random access memory (SRAM) cell.

17 . The memory device of claim 12 , wherein the first interconnect structure and the second interconnect structure are each coupled to respective gate terminals of the plurality of memory cells.

18 . A method for forming a memory device, comprising:
forming a plurality of memory cells in a first area and on a first side of a substrate; forming a first interconnect structure on the first side of the substrate and over the plurality of memory cells, wherein the first interconnect structure are coupled to respective gate terminals of the plurality of memory cells; flipping the substrate; forming a via structure in a second area and on a second side of the substrate, wherein the second area is located next to the first area along a lateral direction; and forming a second interconnect structure on the second side of the substrate, wherein the second interconnect structure is coupled to the first interconnect structure through the via structure; wherein the first interconnect structure and the second interconnect structure each extend along the lateral direction to traverse both the first and second areas.

19 . The method of claim 18 , wherein the via structure extends through the substrate to connect the first side to the second side of the substrate.

20 . The method of claim 18 , wherein the via structure is formed on the second side of the substrate.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Nien Yi-Hsin
• Fujiwara Hidehiro
• Lin Chih-Yu
• Lin Kao-Cheng
• Chen Ying Chih
• Chen Yen-Huei

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• G11C11/412

  using field-effect transistors only · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title