Memory device and method of operating the same

Patent metadata

Field	Value
Publication number	US-2025364038-A1
Application number	US-202519291765-A
Country	US
Kind code	A1
Filing date	Aug 6, 2025
Priority date	Jan 27, 2022
Publication date	Nov 27, 2025
Grant date	—

Abstract

A memory device includes a conductive segment, first and second rows of memory cells. The conductive segment receives a first reference voltage signal. The first row of memory cells is coupled to a first word line. The second row of memory cells is coupled to a second word line. The first row of memory cells includes first and second memory cells. The first memory cell is coupled to the conductive segment to receive the first reference voltage signal. The second row of memory cells includes third and fourth memory cells. The third memory cell is coupled to the conductive segment to receive the first reference voltage signal. The first and third memory cells share the conductive segment, and the third memory cell is arranged between the first and second memory cells. The second memory cell is arranged between the third and fourth memory cells.

First claim

What is claimed is:

1 . A device, comprising:
a first memory cell comprising:
a first switch controlled by a first word line signal and coupled to a first node; and
a second switch coupled between the first node and a second node; and
a second memory cell comprising:
a third switch controlled by a second word line signal different from the first word line signal and coupled to a third node; and
a fourth switch coupled between the third node and the second node.

2 . The device of claim 1 , further comprising:
a third memory cell comprising:
a fifth switch controlled by the first word line signal and coupled to a fourth node; and
a sixth switch coupled between the fourth node and a fifth node different from the second node.

3 . The device of claim 2 , further comprising:
a first resistor, a first terminal of the first resistor being coupled to the second node, and a second terminal of the first resistor being configured to receive a reference voltage signal; and a second resistor, a first terminal of the second resistor being coupled to the fifth node, and a second terminal of the first resistor being configured to receive the reference voltage signal.

4 . The device of claim 2 , further comprising:
a fourth memory cell comprising:
a seventh switch controlled by the first word line signal and coupled to a sixth node; and
an eighth switch coupled between the sixth node and the fifth node.

5 . The device of claim 2 , further comprising:
a seventh switch, a control terminal of the seventh switch being coupled to the first node; and an eighth switch coupled between the seventh switch and a first bit line.

6 . The device of claim 5 , further comprising:
a ninth switch, a control terminal of the ninth switch being coupled to the fourth node; and a tenth switch coupled between the ninth switch and a second bit line, wherein each of a control terminal of the eighth switch and a control terminal of the tenth switch is coupled to a word line.

7 . The device of claim 5 , further comprising:
a ninth switch, a control terminal of the seventh switch being coupled to the third node; and a tenth switch coupled between the ninth switch and the first bit line.

8 . The device of claim 5 , further comprising:
a ninth switch, a control terminal of the ninth switch being coupled to the first node; and a tenth switch coupled between the ninth switch and a second bit line.

9 . A device, comprising:
a first conductive segment configured to provide a first word line signal to a first memory cell; a second conductive segment configured to provide a second word line signal to a second memory cell; a third conductive segment disposed between the first conductive segment and the second conductive segment, and configured to provide a first reference voltage signal to each of the first memory cell and the second memory cell; a fourth conductive segment configured to provide the first word line signal to a third memory cell; and a fifth conductive segment disposed between the second conductive segment and the fourth conductive segment, and configured to provide a second reference voltage signal to each of the third memory cell and the second memory cell.

10 . The device of claim 9 , further comprising:
a first conductive line crossing over each of the first conductive segment, the second conductive segment and the fourth conductive segment, and configured to receive the first word line signal; and a first via coupled to each of the first conductive line and the first conductive segment, and overlapped with the first conductive segment in a layout view.

11 . The device of claim 10 , further comprising:
a second via coupled to each of the first conductive line and the third conductive segment, and overlapped with the third conductive segment in the layout view.

12 . The device of claim 10 , further comprising:
a second conductive line crossing over each of the first conductive segment, the second conductive segment and the fourth conductive segment, and configured to receive the second word line signal; and a second via coupled to each of the second conductive line and the second conductive segment, and overlapped with the second conductive segment in the layout view.

13 . The device of claim 12 , further comprising:
a sixth conductive segment configured to provide the second word line signal to a fourth memory cell; and a seventh conductive segment disposed between the first conductive segment and the sixth conductive segment, and configured to provide the second reference voltage signal to each of the first memory cell and the fourth memory cell.

14 . The device of claim 13 , further comprising:
a third via coupled to each of the second conductive line and the sixth conductive segment, and overlapped with the sixth conductive segment in the layout view.

15 . A method, comprising:
controlling a first switch coupled between a first node and a first bit line by a first word line signal; receiving a first current from a second node by a second switch coupled to the first node; controlling a third switch coupled between a third node and the first bit line by a second word line signal different from the first word line signal; and receiving a second current from the second node by a fourth switch coupled to the first node.

16 . The method of claim 15 , further comprising:
controlling a fifth switch coupled between a fourth node and a second bit line by the first word line signal; and receiving a third current from a fifth node different from the second node by a sixth switch coupled to the fourth node.

17 . The method of claim 16 , further comprising:
receiving a reference voltage signal by a first resistor coupled to the second node; and receiving the reference voltage signal by a second resistor coupled to the fifth node.

18 . The method of claim 17 , wherein the first resistor and the second resistor has the same resistance.

19 . The method of claim 16 , further comprising:
controlling a seventh switch coupled between a sixth node and the second bit line by the second word line signal; and receiving a fourth current from the fifth node by an eighth switch coupled to the fourth node.

20 . The method of claim 15 , wherein a current level of the first current is different from a current level of the second current.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Nien Yi-Hsin
• Fujiwara Hidehiro
• Lin Chih-Yu
• Chen Yen-Huei

Classifications

• H10B10/12

  comprising a MOSFET load element · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title

• G11C8/16

  Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups · CPC title

• G11C11/412 Primary

  using field-effect transistors only · CPC title