Memory devices with switchable power delivery paths

Patent metadata

Field	Value
Publication number	US-2025118632-A1
Application number	US-202318483739-A
Country	US
Kind code	A1
Filing date	Oct 10, 2023
Priority date	Oct 10, 2023
Publication date	Apr 10, 2025
Grant date	—

Abstract

A memory device may comprise a substrate, a plurality of memory cells, and a header device. The substrate may have a first side and a second side opposite to each other. The plurality of memory cells may be formed on the first side of the substrate. The header device may be formed on the first side of the substrate. The header device can be configured to selectively couple a supply voltage through a first combination of power delivery paths or a second combination of power delivery paths to the plurality of memory cells based on a control signal.

First claim

What is claimed is:

1 . A memory device, comprising:
a substrate having a first side and a second side opposite to each other; a plurality of memory cells formed on the first side of the substrate; a header device formed on the first side of the substrate; wherein the header device is configured to selectively couple a supply voltage through a first combination of power delivery paths or a second combination of power delivery paths to the plurality of memory cells based on a control signal.

2 . The memory device of claim 1 , further comprising:
a first conductor structure disposed on the second side of the substrate and configured to provide the supply voltage; a first via structure disposed on the second side of the substrate and configured to electrically couple the first conductor structure to a first source/drain terminal of the header device; a plurality of second via structures disposed on the second side of the substrate and configured to electrically couple the first conductor structure to the memory cells, respectively; a second conductor structure disposed on the first side of the substrate and configured to deliver the supply voltage to the memory cells; a third via structure disposed on the first side of the substrate and configured to electrically couple a second source/drain terminal of the header device to the second conductor structure; and a plurality of fourth via structures disposed on the first side of the substrate and configured to electrically couple the second conductor structure to the memory cells, respectively.

3 . The memory device of claim 2 , wherein the first combination of power delivery paths include:
a first path extending from the first conductor structure, through one of the second via structures, and to one of the memory cells; and a second path extending from the first conductor structure, through the first via structure, the header device, the third via structure, and one of the fourth via structures, and to one of the memory cells.

4 . The memory device of claim 3 , wherein the header device is turned on.

5 . The memory device of claim 2 , wherein the second combination of power delivery paths include:
a path extending from the first conductor structure, through one of the second via structures, and to one of the memory cells.

6 . The memory device of claim 5 , wherein the header device is turned off.

7 . The memory device of claim 1 , wherein the supply voltage is VDD or VSS.

8 . The memory device of claim 2 , wherein the first via structure has a first width extending along a first direction perpendicular to a second direction along which the first conductor structure extends, and the second via structures, the third via structures, and the fourth via structures have a second width extending along the first direction.

9 . The memory device of claim 8 , wherein the first width is substantially greater than the second width.

10 . The memory device of claim 1 , wherein when the control signal is provided at a first logic state, the header device is configured to couple the supply voltage through the first combination of power delivery paths to one or more of the memory cells, and when the control signal is provided at a second logic state, the header device is configured to couple the supply voltage through the second combination of power delivery paths to one or more of the memory cells.

11 . A memory device, comprising:
a plurality of memory cells formed on a frontside of a substrate; a header device also formed on the front side; a first conductor structure disposed on the a backside of the substrate and configured to provide a supply voltage; a first via structure disposed on the backside and configured to electrically couple the first conductor structure to a first source/drain terminal of the header device; a plurality of second via structures disposed on the backside and configured to electrically couple the first conductor structure to the memory cells, respectively; a second conductor structure disposed on the frontside and configured to deliver the supply voltage to the memory cells; a third via structure disposed on the frontside and configured to electrically couple a second source/drain terminal of the header device to the second conductor structure; and a plurality of fourth via structures disposed on the frontside and configured to electrically couple the second conductor structure to the memory cells, respectively.

12 . The memory device of claim 11 , wherein when the header device is turned on, the supply voltage is delivered to one or more of the memory cells through a first path and a second path.

13 . The memory device of claim 12 , wherein the first path extends from the first conductor structure, through respective ones of the second via structures, and to the one or more memory cells, and the second path extends from the first conductor structure, through the first via structure, the header device, the third via structure, the second conductor structure, and respective ones of the fourth via structures, and to the one or more memory cells.

14 . The memory device of claim 11 , wherein when the header device is turned off, the supply voltage is delivered to one or more of the memory cells through a single path.

15 . The memory device of claim 14 , wherein the single path extends from the first conductor structure, through respective ones of the second via structures, and to the one or more memory cells.

16 . The memory device of claim 11 , wherein the header device has p-type conductivity and the supply voltage is VDD.

17 . The memory device of claim 11 , wherein the header device has n-type conductivity and the supply voltage is VSS.

18 . The memory device of claim 11 , wherein the first conductor structure and the second conductor structure each extend along a first direction, the first via structure has a first width extending along a second direction perpendicular to the first direction, each of the second via structures, the third via structure, and the fourth via structures have a second width extending along the second direction, and the first width is substantially greater than the second width.

19 . A method for fabricating memory devices, comprising:
providing a substrate having a first side and a second side opposite to each other; forming a plurality of first transistors and a second transistor on the first side of the substrate; forming a metal structure on the first side of the substrate, wherein the plurality of first transistors and the metal structure are for a plurality of memory cells on the first side of the substrate; wherein the second transistor is for a header device on the first side of the substrate; wherein the second transistor is configured to selectively couple a supply voltage through a first combination of power delivery paths or a second combination of power delivery paths to the plurality of memory cells based on a control signal.

20 . The method of claim 19 , further comprising:
forming a second conductor structure on the first side of the substrate, wherein the second conductor structure is configured to deliver the supply voltage to the first transistors; forming a third via structure on the first side of the substrate, wherein the third via structure is configured to electrically couple a second source/drain terminal of the second transistor to the second conductor structure; and forming a plurality of fourth via structures on the first side of the

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Nien Yi-Hsin
• Lin Chih-Yu
• Fujiwara Hidehiro
• Chen Yen-Huei

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10W20/20 Primary

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H10B10/18

  Peripheral circuit regions · CPC title

• H10B10/12 Primary

  comprising a MOSFET load element · CPC title