Latch circuits and methods for operating the same

Patent metadata

Field	Value
Publication number	US-12531549-B2
Application number	US-202318480751-A
Country	US
Kind code	B2
Filing date	Oct 4, 2023
Priority date	Jun 23, 2023
Publication date	Jan 20, 2026
Grant date	Jan 20, 2026

Abstract

A circuit includes a first Dual Interlocked Storage Cell (DICE) component, a second DICE component, a third DICE component, and a fourth DICE component operatively coupled to one another as a loop. The first and second DICE components form a first sub-latch configured to receive an input signal, the third and fourth DICE components form a second sub-latch configured to receive the same input signal, the first sub-latch is configured to provide, at a first node, an intermediate signal based on the input signal, and the second sub-latch is configured to provide, at a second node, the same intermediate signal based on the input signal. The circuit includes a first inverter configured to logically invert the intermediate signal and provide, at a third node, an output signal. The circuit includes a second inverter configured to logically invert the intermediate signal and provide, at the third node, the output signal.

First claim

What is claimed is:

1 . A circuit, comprising:
a first Dual Interlocked Storage Cell (DICE) component, a second DICE component, a third DICE component, and a fourth DICE component operatively coupled to one another as a loop, wherein the first and second DICE components form a first sub-latch configured to receive an input signal, the third and fourth DICE components form a second sub-latch configured to receive the same input signal, the first sub-latch is configured to provide, at a first node of the first sub-latch, an intermediate signal based on the input signal, and the second sub-latch is configured to provide, at a second node of the second sub-latch, the same intermediate signal based on the input signal; a first inverter configured to logically invert the intermediate signal and provide, at a third node, an output signal; and a second inverter configured to logically invert the intermediate signal and provide, at the third node, the output signal.

2 . The circuit of claim 1 , wherein the first to fourth DICE components are identical to one another.

3 . The circuit of claim 1 , wherein each of the first to fourth DICE components includes a p-type transistor and an n-type transistor.

4 . The circuit of claim 3 , wherein each of the first to fourth DICE components includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal.

5 . The circuit of claim 4 ,
wherein the first input terminal of the first DICE component is a gate of its p-type transistor, the second input terminal of the first DICE component is a common node connecting its p-type transistor and n-type transistor, the first output terminal of the first DICE component is the common node connecting its p-type transistor and n-type transistor, and the second output terminal of the first DICE component is a gate of its n-type transistor; wherein the first input terminal of the second DICE component is a gate of its p-type transistor, the second input terminal of the second DICE component is a common node connecting its p-type transistor and n-type transistor, the first output terminal of the second DICE component is the common node connecting its p-type transistor and n-type transistor, and the second output terminal of the second DICE component is a gate of its n-type transistor; wherein the first input terminal of the third DICE component is a gate of its p-type transistor, the second input terminal of the third DICE component is a common node connecting its p-type transistor and n-type transistor, the first output terminal of the third DICE component is the common node connecting its p-type transistor and n-type transistor, and the second output terminal of the third DICE component is a gate of its n-type transistor; and wherein the first input terminal of the fourth DICE component is a gate of its p-type transistor, the second input terminal of the fourth DICE component is a common node connecting its p-type transistor and n-type transistor, the first output terminal of the fourth DICE component is the common node connecting its p-type transistor and n-type transistor, and the second output terminal of the fourth DICE component is a gate of its n-type transistor.

6 . The circuit of claim 5 , wherein the common node connecting the p-type transistor to the n-type transistor of the second DICE component is the first node of the first sub-latch.

7 . The circuit of claim 6 , wherein the common node connecting the p-type transistor to the n-type transistor of the fourth DICE component is the second node of the second sub-latch.

8 . The circuit of claim 5 , wherein the first input terminal of the first DICE component is the first node of the first sub-latch.

9 . The circuit of claim 8 , wherein the first input terminal of the third DICE component is the second node of the second sub-latch.

10 . The circuit of claim 1 , wherein the first and second sub-latches are each configured to receive the input signal based on a first clock signal and a second clock signal.

11 . The circuit of claim 1 , wherein the first and second sub-latches are each configured to receive the input signal based on a single clock signal.

12 . The circuit of claim 1 , further comprising:
a fifth DICE component and a sixth DICE component, further coupled to the first to fourth DICE components as the loop, wherein the fifth and sixth DICE components form a third sub-latch configured to receive the same input signal, and the third sub-latch is configured to provide, at a fourth node, the same intermediate signal based on the input signal; a third inverter configured to logically invert the intermediate signal and provide, at the third node, the output signal.

13 . A circuit, comprising:
a global input terminal configured to receive an input signal; a global output terminal configured to provide an output signal; a first sub-latch coupled between the global input terminal and the global output terminal, and comprising a first Dual Interlocked Storage Cell (DICE) component and a second DICE component; a second sub-latch coupled between the global input terminal and the global output terminal, and comprising a third DICE component and a fourth DICE component; a first buffer coupled between the first sub-latch and the global output terminal; and a second buffer coupled between the second sub-latch and the global output terminal; wherein the first and third DICE components are configured to be in a first operation state, while the second and fourth DICE components are configured to be in a second, different operation state.

14 . The circuit of claim 13 , wherein each of the first to fourth DICE components includes a p-type transistor and an n-type transistor.

15 . The circuit of claim 14 , wherein each of the first to fourth DICE components includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal.

16 . The circuit of claim 15 ,
wherein the first input terminal of the first DICE component is a gate of its p-type transistor, the second input terminal of the first DICE component is a common node connecting its p-type transistor and n-type transistor, the first output terminal of the first DICE component is the common node connecting its p-type transistor and n-type transistor, and the second output terminal of the first DICE component is a gate of its n-type transistor; wherein the first input terminal of the second DICE component is a gate of its p-type transistor, the second input terminal of the second DICE component is a common node connecting its p-type transistor and n-type transistor, the first output terminal of the second DICE component is the common node connecting its p-type transistor and n-type transistor, and the second output terminal of the second DICE component is a gate of its n-type transistor; wherein the first input terminal of the third DICE component is a gate of its p-type transistor, the second input terminal of the third DICE component is a common node connecting its p-type transistor and n-type transistor, the first output terminal of the third DICE component is the common node connecting its p-type transistor and n-type transistor, and the second output terminal of the third DICE component is a gate of its n-type transistor; and wherein the first input terminal of the fourth DICE component is a gate of its p-type transistor, the second input terminal of the fourth DICE component is a common node connecting its p-type transistor and n-type transistor, the first output terminal of the fourth DICE compone

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Fujiwara Hidehiro
• Li Yu Jung
• Chiang Yueh
• Zhao Wei-Chang
• Nien Yi-Hsin
• Khare Kinshuk

Classifications

• H03K3/037 Primary

  Bistable circuits · CPC title

• H03K3/356191

  with synchronous operation · CPC title

• H03K3/356156

  with synchronous operation · CPC title

• H03K3/0372

  of the primary-secondary type · CPC title

• H03K3/0375 Primary

  provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00) · CPC title