Built-in self test circuit for segmented static random access memory (SRAM) array input/output
US-12584961-B2 · Mar 24, 2026 · US
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Kumar Promod patents
Kumar Promod is listed as an inventor on 55 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Kumar Promod |
| Total patents | 55 |
| First publication | Jun 17, 2021 |
| Latest publication | Mar 24, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Enhanced accuracy of bit line reading for an in-memory compute operation by accounting for variation in read current
US-2026065976-A1 · Mar 5, 2026 · US
Shadow logic on output, at speed test (memory bypass) architecture for memories without input data
US-2026066028-A1 · Mar 5, 2026 · US
Bit line read current mirroring circuit for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (sram)
US-2026065975-A1 · Mar 5, 2026 · US
Memory architecture with a digital in-memory computation processing mode and a column multiplexing memory access mode
US-2026031139-A1 · Jan 29, 2026 · US
At-speed transition fault testing for a multi-port and multi-clock memory
US-2026018228-A1 · Jan 15, 2026 · US
Enhanced accuracy of bit line reading for an in-memory compute operation by accounting for variation in read current
US-12482518-B2 · Nov 25, 2025 · US
Bit line read current mirroring circuit for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)
US-12469545-B2 · Nov 11, 2025 · US
At-speed transition fault testing for a multi-port and multi-clock memory
US-12437825-B2 · Oct 7, 2025 · US
Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (sram)
US-2025308574-A1 · Oct 2, 2025 · US
Recent patents
Latest publications not already listed above.
In-memory computation circuit using static random access memory (SRAM) array segmentation
US-12406705-B2 · Sep 2, 2025 · US
Memory architecture supporting both conventional memory access mode and digital in-memory computation processing mode
US-12361982-B2 · Jul 15, 2025 · US
Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)
US-12354644-B2 · Jul 8, 2025 · US
Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selection
US-12353341-B2 · Jul 8, 2025 · US
Silicon-on-insulator semiconductor device with a static random access memory circuit
US-12328858-B2 · Jun 10, 2025 · US
Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (sram)
US-2025174269-A1 · May 29, 2025 · US
Computing system power management device, system and method
US-12292780-B2 · May 6, 2025 · US
Bit-cell architecture based in-memory compute
US-2025078883-A1 · Mar 6, 2025 · US
Built-in self test circuit for segmented static random access memory (sram) array input/output
US-2025069678-A1 · Feb 27, 2025 · US
Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)
US-12237007-B2 · Feb 25, 2025 · US
Sram with fast, controlled peak current, power efficient array reset, and data corruption modes for secure applications
US-2025054528-A1 · Feb 13, 2025 · US
Sram with fast, controlled peak current, power efficient array reset, and data corruption modes for secure applications
US-2025054529-A1 · Feb 13, 2025 · US
Bit-cell architecture based in-memory compute
US-12183424-B2 · Dec 31, 2024 · US
Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)
US-12176025-B2 · Dec 24, 2024 · US
Built-in self test circuit for segmented static random access memory (SRAM) array input/output
US-12170120-B2 · Dec 17, 2024 · US
SRAM with fast, controlled peak current, power efficient array reset, and data corruption modes for secure applications
US-12159689-B2 · Dec 3, 2024 · US
Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (sram)
US-2024395319-A1 · Nov 28, 2024 · US
Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)
US-12087356-B2 · Sep 10, 2024 · US
Modular memory architecture with gated sub-array operation dependent on stored data content
US-12046324-B2 · Jul 23, 2024 · US
Bit line accumulation readout scheme for an analog in-memory computation processing circuit
US-2024177769-A1 · May 30, 2024 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| St Microelectronics Int Nv | 55 |
| St Microelectronics Srl | 4 |
| St Microelectronics Crolles 2 Sas | 4 |
| St Microelectronics Sa | 1 |
| Stmicroelectronics France | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C11/419 | 37 |
| G11C7/1006 | 33 |
| G11C11/418 | 33 |
| G11C8/08 | 27 |
| G11C7/12 | 23 |