Enhanced accuracy of bit line reading for an in-memory compute operation by accounting for variation in read current

Patent metadata

Field	Value
Publication number	US-12482518-B2
Application number	US-202318137159-A
Country	US
Kind code	B2
Filing date	Apr 20, 2023
Priority date	May 25, 2022
Publication date	Nov 25, 2025
Grant date	Nov 25, 2025

Abstract

An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a read circuit that operates to reduce sensitivity to variation in bit line read current. Additionally, a testing circuit senses analog signals on the complementary bit lines to identify one of the complementary bit lines as having a less variable read current. That identified one of the complementary bit lines is coupled to the read circuit for the in-memory compute operation.

First claim

The invention claimed is:

1 . An in-memory computation circuit, comprising:
a memory array including a plurality of memory cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the memory cells of the row, and each column including a first bit line and second bit line connected to the memory cells of the column; a word line driver circuit for each row having an output connected to drive the word line of the row; a row controller circuit configured to simultaneously actuate the plurality of word lines by applying pulses through the word line driver circuits to the word lines in response to feature data for an in-memory compute operation; and a column processing circuit including a read circuit coupled to the first and second bit lines, wherein each read circuit comprises:
a first sensing circuit comprising a first analog-to-digital converter circuit configured to convert a first bit line signal generated on the first bit line in response to the in-memory compute operation and generate a first digital signal;
a second sensing circuit comprising a second analog-to-digital converter circuit configured to convert a second bit line signal generated on the second bit line in response to the in-memory compute operation and generate a second digital signal; and
a digital signal processing circuit configured to average the first and second digital signals to generate an output signal indicative of a result of the in-memory compute operation.

2 . The circuit of claim 1 , wherein the first and second bit lines are complementary bit lines coupled to the memory cells of the column.

3 . The circuit of claim 1 , wherein the first analog-to-digital converter circuit is configured to implement a first analog-to-digital encoding operation in response to the first bit line signal, wherein the second analog-to-digital converter circuit is configured to implement a second analog-to-digital encoding operation in response to the second bit line signal, and wherein the second analog-to-digital encoding operation is a logical inversion of the first analog-to-digital encoding operation.

4 . An in-memory computation The circuit of claim 1 , comprising:
a memory array including a plurality of memory cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the memory cells of the row, and each column including a first bit line and second bit line connected to the memory cells of the column; a word line driver circuit for each row having an output connected to drive the word line of the row; a row controller circuit configured to simultaneously actuate the plurality of word lines by applying pulses through the word line driver circuits to the word lines in response to feature data for an in-memory compute operation; and a column processing circuit including a read circuit coupled to the first and second bit lines, wherein each read circuit comprises:
an analog-to-digital converter circuit selectively coupled to the first and second bit lines to receive first and second bit line signals, respectively, using a multiplexer circuit and configured to:
convert the first bit line signal generated on the first bit line in response to the in-memory compute operation and generate a first digital sense signal; and
convert the second bit line signal generated on the second bit line in response to the in-memory compute operation and generate a second digital sense signal; and

a digital signal processing circuit configured to average the first and second digital signals to generate an output signal indicative of a result of the in-memory compute operation.

5 . The circuit of claim 4 , wherein said analog-to-digital converter circuit is configured to implement a first analog-to-digital encoding operation in response to the first bit line signal and implement a second analog-to-digital encoding operation in response to the second bit line signal, and wherein the second analog-to-digital encoding operation is a logical inversion of the first analog-to-digital encoding operation.

6 . The circuit of claim 4 , wherein the first and second bit lines are complementary bit lines coupled to the memory cells of the column.

7 . A read method for an in-memory computation circuit, including: a memory array including a plurality of memory cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the memory cells of the row, and each column including a first bit line and second bit line connected to the memory cells of the column; a word line driver circuit for each row having an output connected to drive the word line of the row; and a row controller circuit configured to simultaneously actuate the plurality of word lines by applying pulses through the word line driver circuits to the word lines in response to feature data for an in-memory compute operation, said read method comprising:
performing a first analog-to-digital conversion of a first bit line signal generated on the first bit line in response to the in-memory compute operation to generate a first digital signal; performing a second analog-to-digital conversion of a second bit line signal generated on the second bit line in response to the in-memory compute operation to generate a second digital signal; and averaging the first and second digital signals to generate an output signal indicative of a result of the in-memory compute operation.

8 . The method of claim 7 , wherein the first and second bit lines are complementary bit lines coupled to the memory cells of the column.

9 . The method of claim 7 , wherein the first analog-to-digital conversion is performed using a first encoding operation in response to the first bit line signal, wherein the second analog-to-digital conversion is performed using a second encoding operation in response to the second bit line signal, and wherein the second analog-to-digital encoding operation is a logical inversion of the first analog-to-digital encoding operation.

10 . A read method for an in-memory computation circuit, including: a memory array including a plurality of memory cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the memory cells of the row, and each column including a first bit line and second bit line connected to the memory cells of the column; a word line driver circuit for each row having an output connected to drive the word line of the row; and a row controller circuit configured to simultaneously actuate the plurality of word lines by applying pulses through the word line driver circuits to the word lines in response to feature data for an in-memory compute operation, the method comprising:
selecting the first bit line signal; performing a first analog-to-digital conversion using an analog-to-digital converter circuit to generate a first digital signal; performing a second analog-to-digital conversion using said analog-to-digital converter circuit to generate a second digital signal; and averaging the first and second digital signals to generate an output signal indicative of a result of the in-memory compute operation.

11 . The method of claim 10 , wherein said analog-to-digital converter circuit implements a first analog-to-digital encoding operation when converting the first bit line signal and implements a second analog-to-digital encoding operation when converting the second bit line signal, and wherein the second analog-to-digital encoding operation is a logical inversion of the first analog-to-digital encoding operation.

12 . The method of claim 10 , wherein the

Assignees

• St Microelectronics Int Nv

Inventors

• Dhori Kedar Janardan
• Chawla Nitin
• Kumar Promod
• Rawat Harsh
• Ayodhyawasi Manuj

Classifications

• G11C11/54

  using elements simulating biological cells, e.g. neuron · CPC title

• G06N3/065

  Analogue means · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title

• G11C7/1006 Primary

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C11/4094

  Bit-line management or control circuits · CPC title