Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Patent metadata

Field	Value
Publication number	US-12087356-B2
Application number	US-202217849903-A
Country	US
Kind code	B2
Filing date	Jun 27, 2022
Priority date	Jul 9, 2021
Publication date	Sep 10, 2024
Grant date	Sep 10, 2024

Abstract

SRAM cells are connected in columns by bit lines and connected in rows by first and second word lines coupled to first and second data storage sides of the SRAM cells. First the first word lines are actuated in parallel and then next the second word lines are actuated in parallel in first and second phases, respectively, of an in-memory compute operation. Bit line voltages in the first and second phases are processed to generate an in-memory compute operation decision. A low supply node reference voltage for the SRAM cells is selectively modulated between a ground voltage and a negative voltage. The first data storage side receives the negative voltage and the second data storage side receives the ground voltage during the second phase. Conversely, the second data storage side receives the negative voltage and the first data storage side receives the ground voltage during the first phase.

First claim

What is claimed is:

1. A circuit, comprising:
a memory array storing weight data for an in-memory compute operation and including a plurality of static random access memory (SRAM) cells arranged in a matrix with plural rows and plural columns, each column including a pair of bit lines connected to the SRAM cells of the column, and each row including:
a first word line configured to drive a first passgate transistor of the SRAM cell coupled between a first data storage node of the SRAM cell and one bit line of the pair of bit lines; and
a second word line configured to drive a second passgate transistor of the SRAM cell coupled between a second data storage node of the SRAM cell and another bit line of the pair of bit lines;

a first word line driver circuit for each row having an output connected to drive the first word line of the row;
a second word line driver circuit for each row having an output connected to drive the second word line of the row;
a row controller circuit configured to simultaneously actuate only the first word lines in a first phase of the in-memory compute operation by applying pulses having pulse widths modulated by feature data of the in-memory compute operation through the first word line driver circuits to the first word lines and then simultaneously actuate only the second word lines in a second phase of the in-memory compute operation by applying pulses having pulse widths modulated by feature data of the in-memory compute operation through the second word line driver circuits to the second word lines;
a column processing circuit connected to the pair of bit lines for each column and configured to process analog voltages developed on the pairs of bit lines in response to the first and second phases of the in-memory compute operation to generate a decision output for the in-memory compute operation; and
a source supply modulation circuit configured to independently switch a modulated reference supply voltage for the second and first data storage nodes of the SRAM cells, respectively, from a ground voltage to a negative voltage during the first and second phases of the in-memory compute operation, respectively.

2. The circuit of claim 1 , wherein the source supply modulation circuit is configured to control a level of the negative voltage dependent on integrated circuit process or temperature conditions.

3. The circuit of claim 1 , wherein each SRAM cell comprises a latch circuit having the first data storage node and second data storage node, wherein the latch circuit is configured to receive the modulated reference supply voltage and comprises:
first and second inverters in a cross-coupled configuration having a first output at the first data storage node and a second output at the second data storage node;
wherein the modulated reference supply voltage comprises:
a first modulated reference supply voltage applied to a low supply node of the first inverter; and
a second modulated reference supply voltage applied to a low supply node of the second inverter.

4. The circuit of claim 3 :
wherein the first modulated reference supply voltage has the negative voltage during the second phase of the in-memory compute operation where output of the second data storage node is being read; and
wherein the second modulated reference supply voltage has the negative voltage during the first phase of the in-memory compute operation where output of the first data storage node is being read.

5. The circuit of claim 3 :
wherein the first modulated reference supply voltage has the negative voltage and the second modulated reference supply voltage has the ground voltage during the second phase; and
wherein the second modulated reference supply voltage has the negative voltage and the first modulated reference supply voltage has the ground voltage during the first phase.

6. The circuit of claim 3 , wherein each SRAM cell further comprises:
a first passgate transistor connected to the first data storage node and having a control terminal coupled to the first word line; and
a second passgate transistor connected to the second data storage node and having a control terminal coupled to the second word line;
wherein the first modulated reference supply voltage has the negative voltage and the second modulated reference supply voltage has the ground voltage level when the second wordline is driven during the second phase; and
wherein the second modulated reference supply voltage has the negative voltage and the first modulated reference supply voltage has the ground voltage when the first wordline is driven during the first phase.

7. The circuit of claim 1 , wherein each SRAM cell further comprises:
a first pulldown transistor coupled between the first data storage node and a first low supply node; and
a second pulldown transistor coupled between the second data storage node and a second low supply node;
wherein the source supply modulation circuit is configured to switch the first low supply node from the ground voltage to the negative voltage during the second phase and switch the second low supply node from the ground voltage to the negative voltage during the first phase.

8. The circuit of claim 1 :
wherein the first data storage node on a first side of a latch for the SRAM cell is read during the first phase and the second data storage node on a second side of the latch for the SRAM cell is read during the second phase; and
wherein the source supply modulation circuit is configured to switch a low supply node for the first side of the latch for the SRAM cell from the ground voltage to the negative voltage during the second phase and switch a low supply node for the second side of the latch for the SRAM cell from the ground voltage to the negative voltage during the first phase.

9. The circuit of claim 8 , wherein:
the ground voltage is applied to the low supply node for the first side of the latch for the SRAM cell during the first phase; and
the ground voltage is applied to the low supply node for the second side of the latch for the SRAM cell during the second phase.

10. The circuit of claim 1 , wherein the source supply modulation circuit includes a voltage boosting circuit configured to boost the modulated reference supply voltage from the ground voltage to the negative voltage in response to a control signal that is indicative of performance of each of the first and second phases.

11. The circuit of claim 10 , wherein the boost of the modulated reference supply voltage is provided by a capacitive voltage boosting circuit comprising:
a transistor having a source coupled to receive the ground voltage, a drain coupled to a low power supply node of the SRAM cell and a gate configured to receive the control signal; and
a capacitor having a first terminal coupled to the gate and a second terminal coupled to the drain.

12. The circuit of claim 11 , further comprising:
a switch coupled in series with the capacitor between the gate and drain; and
a control circuit configured to selectively actuate the switch, wherein the control circuit selectively actuates said switch in response to information concerning integrated circuit process and/or temperature conditions in order to set a level of the negative voltage.

13. The circuit of claim 10 , wherein the boost of the modulated reference supply voltage is provided by a capacitive voltage boosting circuit comprising:
a transistor having a source coupled to receive the ground voltage, a drain coupled to a low power supply node of the SRAM cell and a gate configured to receive the control signal;
a plurality of switched capacitor circuits coupled in parallel between the

Assignees

• St Microelectronics Int Nv

Inventors

• Rawat Harsh
• Dhori Kedar Janardan
• Kumar Promod
• Chawla Nitin
• Ayodhyawasi Manuj

Classifications

• G11C11/417

  for memory cells of the field-effect type · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C8/12

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C11/418 Primary

  Address circuits · CPC title