Silicon-on-insulator semiconductor device with a static random access memory circuit

Patent metadata

Field	Value
Publication number	US-12328858-B2
Application number	US-202318347435-A
Country	US
Kind code	B2
Filing date	Jul 5, 2023
Priority date	Jul 6, 2022
Publication date	Jun 10, 2025
Grant date	Jun 10, 2025

Abstract

In one embodiment, a semiconductor device includes a carrier substrate, a buried dielectric region overlying the carrier substrate, and a semiconductor film separated from the carrier substrate by the buried dielectric region. NMOS transistors and PMOS transistors are disposed at a surface of the semiconductor film and coupled together to form a static random access memory (SRAM) cell. The NMOS transistors and the PMOS transistors each include a gate dielectric layer having a thickness greater than three nanometers and an active region in the semiconductor film. The active region of the PMOS transistors are formed from a silicon-germanium alloy.

First claim

What is claimed is:

1. A semiconductor device comprising:
a carrier substrate;
a buried dielectric region overlying the carrier substrate;
a semiconductor film separated from the carrier substrate by the buried dielectric region; and
NMOS transistors and PMOS transistors disposed at a surface of the semiconductor film and coupled together to form a static random access memory (SRAM) cell, the NMOS transistors and the PMOS transistors each comprising a gate dielectric layer having a thickness greater than 3 nanometers and an active region in the semiconductor film, the active region of the PMOS transistors comprising a silicon-germanium alloy.

2. The device according to claim 1 , wherein the gate dielectric layers of the NMOS transistors and of the PMOS transistors have a thickness, taken between the active region and a gate conductive region, between 3.5 nanometers and 6 nanometers.

3. The device according to claim 1 , further comprising a plurality of further PMOS transistors each having an active region being made of the silicon-germanium alloy, wherein the active regions of a plurality of the PMOS transistor extend along a first direction.

4. The device according to claim 3 , wherein the further PMOS transistors are coupled to further NMOS transistors to form further SRAM cells, wherein the active regions of the further PMOS transistors and active regions of the NMOS transistors extend along the first direction so as to incorporate other SRAM cells.

5. The device according to claim 3 , wherein the active regions of the plurality of the PMOS transistors extend along the first direction so as to not relax a compression stress in the first direction of the silicon-germanium alloy.

6. The device according to claim 1 , wherein the NMOS transistors and the PMOS transistors are located in respectively doped wells of the carrier substrate, the device further comprising a bias circuit coupled to the doped wells of the carrier substrate.

7. The device according to claim 6 , wherein the bias circuit is configured to generate, in the respectively doped wells of the carrier substrate, voltages adapted for reverse back biases of the PMOS and NMOS transistors.

8. The device according to claim 6 , wherein the NMOS transistors are located in p-type doped wells in the carrier substrate, the PMOS transistors are located in n-type doped wells in the carrier substrate.

9. The device according to claim 8 , wherein the bias circuit is configured to generate a reverse back bias voltage between 0 volts and −2 volts in the p-type doped wells.

10. The device according to claim 8 , wherein the bias circuit is configured to generate a reverse back bias voltage between 0 volts and +2 volts in the n-type doped wells.

11. The device according to claim 6 , wherein the bias circuit is configured to generate voltages adapted for reverse back biases of the PMOS and NMOS transistors, in a mode for retention of a piece of data of the memory cell and not in a read-write mode of the memory cell.

12. The device according to claim 6 , wherein the bias circuit is configured to generate a power supply voltage for the memory cell having a nominal level in a read-write mode and a voltage of 50% to 85% of the nominal level in a mode for retention of a piece of data.

13. A method of operating a static random access memory formed from NMOS transistors and PMOS transistors disposed a surface of a semiconductor film that is separated from a carrier substrate by a buried dielectric region, wherein the NMOS transistors and the PMOS transistors each comprise a gate dielectric layer having a thickness greater than 3 nanometers and an active region in the semiconductor film and wherein the active region of the PMOS transistors comprises a silicon-germanium alloy, the method comprising:
operating the memory in a read-write mode, wherein the NMOS transistors and the PMOS transistors are back biased to a nominal voltage in the read-write mode; and
operating the memory in a retention mode, wherein the NMOS transistors and the PMOS transistors are back biased to a voltage that is 50% to 85% of the nominal voltage in the retention mode.

14. The method of claim 13 , further comprising applying a reverse back bias voltage between 0 volts and −2 volts to p-type doped wells of the NMOS transistors.

15. The method of claim 13 , further comprising applying a reverse back bias voltage between 0 volts and +2 volts to n-type doped wells of the PMOS transistors.

16. A method of forming a semiconductor device in a semiconductor film separated from a carrier substrate by a buried dielectric region, the method comprising:
forming NMOS transistors and PMOS transistors at a surface of the semiconductor film; and
coupling the NMOS transistors and the PMOS transistors together to form a plurality of static random access memory (SRAM) cells;
wherein the NMOS transistors and the PMOS transistors each comprise a gate dielectric layer having a thickness greater than 3 nanometers;
wherein the NMOS transistors comprise an active region of silicon in the semiconductor film; and
wherein the PMOS transistors comprise an active regions of a silicon-germanium alloy in the semiconductor film.

17. The method according to claim 16 , wherein forming the NMOS transistors and the PMOS transistors comprises:
modifying a silicon film in an area of the active regions of the PMOS transistors to form the silicon-germanium alloy;
forming shallow isolation trenches to define the active regions;
forming n-type doped wells of the PMOS transistors in the carrier substrate;
forming p-type doped wells of the NMOS transistors in the carrier substrate;
forming the gate dielectric layer;
forming a gate conductive layer over the gate dielectric layer;
patterning the gate conductive layer to form gate conductive regions;
forming source and drain regions for the NMOS transistors and the PMOS transistors; and
interconnecting the NMOS transistors and the PMOS transistors to form the SRAM cells.

18. The method according to claim 17 , wherein modifying the silicon film comprises implementing a condensation technique.

19. The method according to claim 17 , wherein the gate dielectric layer is formed to a thickness between 3.5 nm and 6 nm.

20. The method according to claim 16 , wherein the active regions are formed so as to extend along a first direction so as to incorporate a plurality of the SRAM cells.

21. The method according to claim 20 , wherein the active regions are formed so as to extend along the first direction so as to not relax a compression stress in the first direction of the silicon-germanium alloy.

22. The method according to claim 16 , further comprising manufacturing a bias circuit electrically coupled to n-type doped wells of the PMOS transistors and p-type doped wells of the NMOS transistors.

Assignees

• Stmicroelectronics France
• St Microelectronics Crolles 2 Sas
• St Microelectronics Int Nv

Inventors

• Weber Olivier
• Dhori Kedar Janardan
• Kumar Promod
• Ahmed Shafquat Jahan
• Lecocq Christophe
• Urard Pascal

Classifications

• H10D30/0323

  comprising monocrystalline silicon · CPC title

• G11C11/417

  for memory cells of the field-effect type · CPC title

• H10B10/18

  Peripheral circuit regions · CPC title

• H10D30/6744

  Monocrystalline silicon · CPC title

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title