SRAM with fast, controlled peak current, power efficient array reset, and data corruption modes for secure applications

Patent metadata

Field	Value
Publication number	US-12159689-B2
Application number	US-202217853026-A
Country	US
Kind code	B2
Filing date	Jun 29, 2022
Priority date	Jul 13, 2021
Publication date	Dec 3, 2024
Grant date	Dec 3, 2024

Abstract

A method of corrupting contents of a memory array includes asserting a signal at a reset node to thereby cause starving of current supply to the memory array, and selecting bit lines and complementary bit lines associated with desired columns of the memory array that contain memory cells to have their contents corrupted. For each desired column, a logic state of its bit line and complementary bit line are forced to a same logic state. Each word line associated with desired rows of the memory array that contains memory cells to have their contents corrupted is simultaneously asserted, and then simultaneously deasserted to thereby place each memory cell to have its contents corrupted into a metastable state during a single clock cycle.

First claim

The invention claimed is:

1. A method of resetting contents of a memory array, comprising:
a) asserting a signal at a reset node to thereby cause starving of current supply to the memory array, the signal at the reset node being a complement of an internal clock signal;
b) selecting bit lines and complementary bit lines associated with desired columns of the memory array that contain memory cells to have their contents reset;
c) for each desired column, forcing a logic state of its bit line and complementary bit line to opposite logic states; and
d) simultaneously asserting each word line associated with desired rows of the memory array that contains memory cells to have their contents reset, and then simultaneously deasserting those word lines to thereby set the contents of the memory cells to have their contents reset to be a desired logic value that is a function of the opposite logic states of their bit lines and their complementary bit lines.

2. The method of claim 1 ,
further comprising:
generating a virtual supply voltage from a power supply voltage by coupling a power supply voltage node to a virtual supply voltage node using multiple transistors to thereby generate the virtual supply voltage at the virtual supply voltage node; and
powering the memory array using the virtual supply voltage;

wherein asserting the signal at the reset node causes starving of the current supply to the memory array by turning off one of the multiple transistors being used to couple the power supply voltage node to the virtual supply voltage node.

3. The method of claim 2 , wherein the opposite logic states are different for different desired columns such that different desired columns have their contents reset to different desired logic values, or the opposite logic states are the same for the desired columns such that the desired columns each have their contents reset to a same desired logic value.

4. The method of claim 2 ,
wherein all memory cells of the memory array are desired to have their contents reset;
wherein b) comprises selecting all bit lines and all complementary bit lines;
wherein c) comprises, for each column, forcing a logic state of its bit line and complementary bit line to opposite logic states; and
wherein d) comprises simultaneously asserting each word line, and then simultaneously deasserting each word line.

5. The method of claim 4 , wherein c) comprises, for each column, forcing a logic state of its bit line to a first logic state and forcing a logic state of its complementary bit line to a second logic state.

6. The method of claim 1 , wherein less than all memory cells of the memory array are desired to have their contents reset.

7. A method of performing a fast reset of memory cells in an SRAM device to a logic reset state, the SRAM device powered between a virtual supply voltage node and a ground node, the method comprising:
generating a virtual supply voltage at the virtual supply voltage node from a primary supply voltage node using a supply voltage generation circuit, the supply voltage generation circuit including a first transistor and a second transistor coupled between the primary supply voltage node and the virtual supply voltage node;
turning off the first transistor to limit current supplied to the virtual supply voltage node when a complement of an internal clock signal is asserted;
asserting one or more word lines to access memory cells in one or more rows of the SRAM device;
forcing bit lines associated with one or more columns of the SRAM device to the logic reset state logic low; and
writing the logic reset state to the accessed memory cells.

8. The method of claim 7 , further comprising deasserting the complement of the internal clock signal to turn on the first transistor and increase the current supplied to the virtual supply voltage node.

9. The method of claim 7 , further comprising supplying a greater amount of current to the virtual supply voltage node using the first transistor than using the second transistor because the first transistor is larger than the second transistor.

10. The method of claim 7 , wherein forcing the bit lines associated with the one or more columns of the SRAM device to the logic reset state comprises:
clocking multiplexers to select a latched version of a reset signal; and
passing the latched version of the reset signal through the multiplexers and inverters to force the bit lines to the logic reset state logic low.

11. The method of claim 10 , wherein the SRAM device comprises a column decoder and a row decoder, and wherein asserting the one or more word lines comprises:
providing the latched version of the reset signal to the column decoder to select the one or more columns; and
providing the latched version of the reset signal to the row decoder to select the one or more rows.

12. The method of claim 7 , wherein asserting the one or more word lines comprises asserting word lines associated with all rows of the SRAM device such that the logic reset state is written to all memory cells in the SRAM device.

13. The method of claim 7 , further comprising:
precharging the bit lines using precharge circuitry prior to forcing the bit lines to the logic reset state.

14. A method of resetting contents of a memory array, comprising:
a) asserting a signal at a reset node to thereby cause starving of current supply to the memory array;
b) selecting bit lines and complementary bit lines associated with desired columns of the memory array that contain memory cells to have their contents reset;
c) for each desired column, forcing a logic state of its bit line and complementary bit line to opposite logic states, wherein forcing the logic state of the bit line and complementary bit line of each desired column to opposite logic states is performed by causing multiplexers to pass the signal from the reset node to the bit lines and complementary bit lines, and inverting the signal passed to the bit lines such that the bit lines are forced to a logic low state and the complementary bit lines are forced to a logic high state when the reset node is asserted; and
d) simultaneously asserting each word line associated with desired rows of the memory array that contains memory cells to have their contents reset, and then simultaneously deasserting those word lines to thereby reset the contents of the memory to a desired logic value that is a function of the opposite logic states of their bit lines and their complementary bit lines.

15. The method of claim 14 ,
further comprising:
generating a virtual supply voltage from a power supply voltage by coupling a power supply voltage node to a virtual supply voltage node using multiple transistors to thereby generate the virtual supply voltage at the virtual supply voltage node; and
powering the memory array using the virtual supply voltage;

wherein asserting the signal at the reset node causes starving of the current supply to the memory array by turning off one of the multiple transistors being used to couple the power supply voltage node to the virtual supply voltage node.

16. The method of claim 15 , wherein the opposite logic states are different for different desired columns such that different desired columns have their contents reset to different desired logic values, or the opposite logic states are the same for the desired columns such that the desired columns each have their contents reset to a same desired logic value.

17. The method of claim 15 ,
wherein all memory cells of the memory array are desired to have their contents reset;
wherein b

Assignees

• St Microelectronics Int Nv

Inventors

• Verma Praveen Kumar
• Kumar Promod
• Rawat Harsh

Classifications

• G11C11/418 Primary

  Address circuits · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C5/147

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title