Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selection

Patent metadata

Field	Value
Publication number	US-12353341-B2
Application number	US-202318379373-A
Country	US
Kind code	B2
Filing date	Oct 12, 2023
Priority date	Oct 26, 2022
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

A memory circuit includes an array of memory cells arranged in rows and columns. A word line is connected to the memory cells of each row. A row decoder circuit operates in response to an internal clock and an address to selectively apply a word line signal to one word line and further generate a dummy word line signal. A control circuit includes a clock generator that generates the internal clock which is reset in response to a reset signal. A first delay circuit receives the dummy word line signal and outputs a first delayed dummy word line signal. A second delay circuit receives the dummy word line signal and outputs a second delayed dummy word line signal. A multiplexer circuit selects between the first and second delayed dummy word line signals for output as the reset signal in response to a logic state of a mode control signal.

First claim

The invention claimed is:

1. A memory circuit, comprising:
a memory array including memory cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the memory cells of the row, and each column including a bit line connected to memory cells of the column;
a row decoder circuit operating in response to an internal clock and a received address to selectively actuate one of the word lines with a word line signal through a word line driver and further actuate a dummy word line with a dummy word line signal through a dummy word line driver; and
a control circuit comprising:
a clock generator configured to generate said internal clock, wherein said internal clock is reset in response to a reset signal;
a first delay circuit receiving the dummy word line signal from the dummy word line and outputting a first delayed dummy word line signal;
a second delay circuit receiving the dummy word line signal from the dummy word line and outputting a second delayed dummy word line signal; and
a first multiplexer circuit configured to receive the first and second delayed dummy word line signals and select said first delayed dummy word line signal for output as said reset signal in response to a first logic state of a mode control signal and select said second delayed dummy word line signal for output as said reset signal in response to a second logic state of the mode control signal.

2. The memory circuit of claim 1 , wherein said first and second delay circuits set delays for a memory write cycle time, wherein a first delay time provided by the first delay circuit is longer than a second delay time provided by the second delay circuit.

3. The memory circuit of claim 2 , wherein said control circuit further comprises a second multiplexer circuit configured to selectively pass the selected one of the first and second delayed dummy word line signals as the reset signal when said memory circuit is configured for operation in write mode.

4. The memory circuit of claim 1 , wherein said first and second delay circuits set delays for a memory read cycle time, wherein a first delay time provided by the first delay circuit is shorter than a second delay time provided by the second delay circuit.

5. The memory circuit of claim 4 , wherein said control circuit further comprises a second multiplexer circuit configured to selectively pass the selected one of the first and second delayed dummy word line signals as the reset signal when said memory circuit is configured for operation in read mode.

6. The memory circuit of claim 1 , wherein the memory cells are 6T static random access memory cells.

7. The memory circuit of claim 1 , wherein the memory cells are 8T static random access memory cells.

8. A memory circuit, comprising:
a memory array including memory cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the memory cells of the row, and each column including a bit line connected to memory cells of the column;
a row decoder circuit operating in response to an internal clock and a received address to selectively actuate one of the word lines with a word line signal through a word line driver and further actuate a dummy word line with a dummy word line signal through a dummy word line driver; and
a control circuit comprising:
a clock generator configured to generate said internal clock, wherein said internal clock is reset in response to a reset signal;
a first delay circuit receiving the dummy word line signal from the dummy word line and outputting a first delayed dummy word line signal;
a second delay circuit receiving the dummy word line signal from the dummy word line and outputting a second delayed dummy word line signal;
a first multiplexer circuit configured to receive the first and second delayed dummy word line signals and select said first delayed dummy word line signal for output as a write reset signal in response to a first logic state of a mode control signal and select said second delayed dummy word line signal for output as said write reset signal in response to a second logic state of the mode control signal;
a third delay circuit receiving the dummy word line signal from the dummy word line and outputting a third delayed dummy word line signal;
a fourth delay circuit receiving the dummy word line signal from the dummy word line and outputting a fourth delayed dummy word line signal;
a second multiplexer circuit configured to receive the third and fourth delayed dummy word line signals and select said third delayed dummy word line signal for output as a read reset signal in response to the first logic state of the mode control signal and select said fourth delayed dummy word line signal for output as said read reset signal in response to the second logic state of the mode control signal.

9. The memory circuit of claim 8 , wherein a first delay time provided by the first delay circuit is longer than a second delay time provided by the second delay circuit.

10. The memory circuit of claim 8 , wherein a third delay time provided by the third delay circuit is shorter than a fourth delay time provided by the fourth delay circuit.

11. The memory circuit of claim 8 , wherein a first delay time provided by the first delay circuit is longer than a second delay time provided by the second delay circuit, and wherein a third delay time provided by the third delay circuit is shorter than a fourth delay time provided by the fourth delay circuit.

12. The memory circuit of claim 8 , wherein said control circuit further comprises a third multiplexer circuit configured to selectively pass the selected one of the first and second delayed dummy word line signals as the reset signal when said memory circuit is configured for operation in write mode and to selectively pass the selected one of the third and fourth delayed dummy word line signals as the reset signal when said memory circuit is configured for operation in read mode.

13. The memory circuit of claim 8 , wherein the memory cells are 6T static random access memory cells.

14. The memory circuit of claim 8 , wherein the memory cells are 8T static random access memory cells.

15. A method, comprising:
generating an internal clock signal having a leading edge controlled by an edge of an external clock and a trailing edge controlled by a reset signal;
asserting a dummy word line signal for application to a memory circuit in response to the internal clock signal;
applying a first delay time to the dummy word line signal to generate a first delayed dummy word line signal;
applying a second delay time to the dummy word line signal to generate a second delayed dummy word line signal;
selecting the first delayed dummy word line signal for output as said reset signal in response to a first logic state of a mode control signal; and
selecting the second delayed dummy word line signal for output as said reset signal in response to a second logic state of the mode control signal.

16. The method of claim 15 , wherein said first and second delay times set delays for a memory write cycle time, wherein the first delay time is longer than the second delay time.

17. The method of claim 16 , further comprising selectively passing the selected one of the first and second delayed dummy word line signals as the reset signal when said memory circuit is configured for operation in write mode.

18. The method of claim 15 , wherein said first and second delay times set delays for a memory read cycle time, wherein the first delay time i

Assignees

• St Microelectronics Int Nv

Inventors

• Singh Bhupender
• Chawla Hitesh
• Kumar Tanuj
• Rawat Harsh
• Dhori Kedar Janardan
• Kumar Promod
• Ayodhyawasi Manuj
• Chawla Nitin

Classifications

• G06F3/061

  Improving I/O performance · CPC title

• G06F3/0655

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F3/0673

  Single storage device · CPC title

• G11C11/418

  Address circuits · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title