Modular memory architecture with gated sub-array operation dependent on stored data content

Patent metadata

Field	Value
Publication number	US-12046324-B2
Application number	US-202217861458-A
Country	US
Kind code	B2
Filing date	Jul 11, 2022
Priority date	Aug 11, 2021
Publication date	Jul 23, 2024
Grant date	Jul 23, 2024

Abstract

A memory circuit includes an array of memory cells arranged with first word lines connected to a first sub-array storing less significant bits of data and second word lines connected to a second sub-array storing more significant bits of data. A row decoder circuit coupled to the first and second word lines generates word line signals. A word line gating circuit is configured to selectively gate passage of the word line signals to the second word lines for the second sub-array in response to assertion of a maximum value signal. A data modification circuit performs a mathematical operation on data read from the array of memory cells, and asserts the maximum value signal if the mathematical operation performed on the less significant bits of data from the first sub-array produces a maximum data value.

First claim

What is claimed is:

1. A circuit, comprising:
a memory circuit including:
a memory core formed by an array of memory cells storing data words at rows, wherein each row is connected to a word line, and wherein said array is arranged to include a first sub-array storing less significant bits of said data words and a second sub-array storing more significant bits of said data words; and
a row decoder circuit configured to receive an address, decode the received address and generate a word line signal that is applied to a selected one of the word lines for a certain data location based on the decoded address;

a data modification circuit configured to perform a mathematical operation on a data word read from said certain data location in the array of memory cells corresponding to the selected one of the word lines in order to produce a modified data word that is written back to that certain data location in the array of memory cells;
wherein the row decoder further includes a word line gating circuit configured to selectively gate passage of the word line signal to memory cells of the second sub-array in response to assertion of a maximum value signal; and
a detection circuit configured to assert said maximum value signal in response to a determination that the mathematical operation performed on the less significant bits of said data word from the first sub-array produces a maximum data value for the less significant bits of said data word.

2. The circuit of claim 1 , wherein said data modification circuit is external to the memory circuit.

3. The circuit of claim 1 , wherein said data modification circuit is internal to the memory circuit.

4. The circuit of claim 1 , wherein the mathematical operation comprises one of an increment operation, a decrement operation or a multiply operation.

5. The circuit of claim 1 , wherein the word line gating circuit comprises a logical AND gate for each word line, said logical AND gate including a first input configured to receive the word line signal, a second input configured to receive a gating control signal derived from said maximum value signal and an output coupled to the word line for the memory cells of the second sub-array.

6. The circuit of claim 1 , wherein the word line gating circuit comprises:
a logical AND gate for each word line, said logical AND gate including a first input configured to receive the word line signal, a second input configured to receive a gating control signal and an output coupled to the word line for the memory cells of the second sub-array; and
a latching circuit configured to selectively latch the gating control signal in response to assertion of the maximum value signal.

7. The circuit of claim 6 , wherein said latching circuit comprises:
a set-reset latch having a set input configured to receive the maximum value signal and a clock input; and
a further logical AND gate including a first input configured to receive a word line select signal, a second input configured to receive a clocking signal and an output coupled to the clock input of the set-reset latch.

8. The circuit of claim 1 , wherein the word line gating circuit comprises:
a logical AND gate for each word line, said logical AND gate including a first input configured to receive the word line signal, a second input configured to receive a gating control signal and an output coupled to the word line for the memory cells of the second sub-array; and
a maximum value address circuit configured in response to assertion of the maximum value signal to store addresses associated with data locations where the mathematical operation performed on the less significant bits of said data word from the first sub-array produces the maximum data value, said maximum value address circuit further configured to output said gating control signal when the memory is addressed at one of the stored addresses.

9. The circuit of claim 8 , wherein the memory further comprises input/output circuitry coupled to the memory core, and wherein said input/output circuitry is configured to read the data words for output from only the data location corresponding to the stored address.

10. The circuit of claim 8 , wherein the maximum value address circuit is further configured to flag one of the stored addresses whose data word has a highest value, and wherein said input/output circuitry is configured to read the data word for output from only the data location for the stored address that has been flagged.

11. The circuit of claim 1 , wherein the memory further comprises:
first input/output circuitry coupled to the first sub-array;
second input/output circuitry coupled to the second sub-array; and
a control circuit configured to generate control signals for controlling operation of circuits within said first input/output circuitry and said second input/output circuitry;
wherein said control circuit comprises a control signal gating circuit configured to selectively gate passage of the control signals to the second input/output circuitry in response to assertion of said maximum value signal.

12. The circuit of claim 1 , wherein said data modification circuit comprises a plurality of adder circuits in series configured to perform the mathematical operation, and wherein the detection circuit is configured to assert the maximum value signal if output from all of the adder circuits is in a same logic state.

13. The circuit of claim 1 , wherein the word line gating circuit permits access to all rows of the second sub-array storing more significant bits of said data words in response to assertion of the maximum value signal.

14. The circuit of claim 1 , wherein the word line gating circuit permits access to only those certain rows of the second sub-array storing more significant bits of said data words for data locations where the maximum value signal was asserted by the detection circuit due to the mathematical operation performed on the less significant bits from the first sub-array producing the maximum data value.

15. The circuit of claim 1 , wherein the memory circuit is further configured to operate in a data read mode of operation to retrieve data words, and wherein the word line gating circuit is further configured to gate passage of a word line signal in the data read mode of operation to access memory cells of the second sub-array.

16. A circuit, comprising:
a memory circuit including:
an array of memory cells arranged to include a first sub-array storing less significant bits of data and a second sub-array storing more significant bits of data;
a first plurality of word lines for the first sub-array;
a second plurality of word lines for the second sub-array; and
a row decoder circuit coupled to the first and second pluralities of word lines, wherein said row decoder generates word line signals and includes a word line gating circuit configured to selectively gate passage of said word line signals to the second plurality of word lines for the second sub-array in response to assertion of a maximum value signal;

a data modification circuit configured to perform a mathematical operation on data read from the array of memory cells; and
a detection circuit configured to assert said maximum value signal in response to the mathematical operation performed on the less significant bits of data from the first sub-array producing a maximum data value.

17. The circuit of claim 16 , wherein said data modification circuit and detection circuit are external to the memory circuit.

18. The circuit of claim 16 , wherein said data modification circuit an

Assignees

• St Microelectronics Int Nv
• St Microelectronics Crolles 2 Sas

Inventors

• Rawat Harsh
• Verma Praveen Kumar
• Kumar Promod
• Lecocq Christophe

Classifications

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C7/1087

  Data input latches · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C5/005

  Circuit means for protection against loss of information of semiconductor storage devices · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title