Memory architecture supporting both conventional memory access mode and digital in-memory computation processing mode

Patent metadata

Field	Value
Publication number	US-12361982-B2
Application number	US-202318233562-A
Country	US
Kind code	B2
Filing date	Aug 14, 2023
Priority date	Aug 30, 2022
Publication date	Jul 15, 2025
Grant date	Jul 15, 2025

Abstract

The memory array of a circuit includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports two modes of circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. In memory computation operations are performed in the second mode as a function of feature data and weight data stored in the memory.

First claim

What is claimed is:

1. A circuit, comprising:
a memory array including a plurality of sub-arrays, wherein each sub-array includes memory cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the memory cells of the row, and each column including a local bit line connected to the memory cells of the column;
a word line drive circuit for each row having an output connected to drive the word line of the row;
a row decoder circuit coupled to the word line drive circuits;
a control circuit configured to support two modes of memory circuit operation including: a first mode where the row decoder circuit actuates only one word line in the memory array during a memory access operation and a second mode where the row decoder circuit simultaneously actuates one word line per sub-array during an in-memory computation operation;
an input/output circuit for each column comprising:
a plurality of bit line inputs coupled to the local bit lines of the sub-arrays;
a column data output coupled to the plurality of bit line inputs and configured to generate a column data bit for output in the first mode;
a computation circuit configured to store feature data and perform a computational operation as a function of the feature data and a plurality of sub-array data bits present at the plurality of bit line inputs to generate a plurality of partial computation data bits; and
a plurality of sub-array data outputs coupled to the computation circuit and configured to output the plurality of partial computation data bits in the second mode.

2. The circuit of claim 1 , further comprising a processing circuit coupled to the plurality of sub-array data outputs and configured to process the plurality of partial computation data bits.

3. The circuit of claim 1 , wherein the computational operation is a Boolean operation.

4. The circuit of claim 3 , wherein the Boolean operation is selected from a group consisting of an XOR operation, an XNOR operation, a NAND operation and a NOR operation.

5. The circuit of claim 1 , wherein the computational operation is a vector processing operation.

6. The circuit of claim 1 , wherein the control circuit is configured to generate a mask signal, and wherein performance of the computation operation for each sub-array data bit is selectively enabled in response to the mask signal.

7. The circuit of claim 1 , wherein each memory cell is a static random access memory (SRAM) cell.

8. The circuit of claim 7 , wherein the SRAM cell is an 8T-type cell, wherein the word line is a read word line of the 8T-type cell and the local bit line is a read bit line of the 8T-type cell.

9. The circuit of claim 7 , wherein the SRAM cell is a 6T-type cell, wherein the word line is a word line of the 6T-type cell and the local bit line is one bit line of a complementary pair of bit lines for the 6T-type cell.

10. The circuit of claim 1 , wherein each memory cell is a non-volatile memory cell with a deterministic output.

11. The circuit of claim 1 , wherein the input/output circuit for each column further comprises:
between each bit of the plurality of computation bits and the corresponding sub-array data output, a first latch circuit and a first buffer circuit; and
a first multiplexing circuit having a first input coupled to receive a bit of the plurality of computation bits, an output coupled to the first latch circuit and the first buffer circuit, and a second input coupled to the output of the first multiplexing circuit;
wherein a selection input of the first multiplexing circuit is configured to receive a mode control signal, the first multiplexing circuit selecting the second input when the mode control signal is in a first state corresponding to the first mode and selecting the first input when the mode control signal is in a second state corresponding to the second mode.

12. The circuit of claim 11 , wherein the input/output circuit for each column further comprises a read circuit coupled between the bit line input and the first input of the first multiplexing circuit.

13. The circuit of claim 11 , wherein the input/output circuit for each column further comprises:
between the plurality of bit line inputs and the column data output, a second latch circuit and a second buffer circuit; and
a second multiplexing circuit having a first input coupled the plurality of bit line inputs, an output coupled to the second latch circuit and the second buffer circuit, and a second input coupled to the output of the second multiplexing circuit;
wherein a selection input of the second multiplexing circuit is configured to receive the mode control signal, the second multiplexing circuit selecting the first input when the mode control signal is in the first state corresponding to the first mode and selecting the second input when the mode control signal is in the second state corresponding to the second mode.

14. The circuit of claim 13 , wherein the input/output circuit for each column further comprises a read circuit coupled between the plurality of bit line inputs and the first input of the second multiplexing circuit.

15. The circuit of claim 1 :
wherein the row decoder circuit comprises a plurality of sub-decoder circuits corresponding to the plurality of sub-arrays;
wherein the control circuit is configured to receive an address and includes a predecoder circuit configured to predecode the address and generate decoder control signals for application to the plurality of sub-decoder circuits; and
wherein each sub-decoder circuit selectively generates a word line signal on a word line in response to said decoder control signals.

16. The circuit of claim 15 , wherein in the first mode only one of the plurality of sub-decoder circuits generates one word line signal and wherein in the second mode each of the plurality of sub-decoder circuits generates one word line signal on a word line.

17. The circuit of claim 16 , wherein the control circuit is configured to generate a mask signal, and wherein each of the plurality of sub-decoder circuits is selectively enabled for generating the one word line signal in response to the mask signal.

18. The circuit of claim 1 :
wherein the row decoder circuit comprises a plurality of sub-decoder circuits corresponding to the plurality of sub-arrays;
wherein the control circuit is configured, in the first mode, to receive a first address and includes a first predecoder circuit configured to predecode the first address and generate decoder control signals for application to the plurality of sub-decoder circuits; and
wherein only one of the plurality of sub-decoder circuits generates one word line signal on a word line in response to said decoder control signals.

19. The circuit of claim 1 :
wherein the row decoder circuit comprises a plurality of sub-decoder circuits corresponding to the plurality of sub-arrays;
wherein the control circuit is configured, in the second mode, to receive a plurality of second addresses corresponding to the plurality of sub-decoder circuits and includes a second predecoder circuit configured to predecode the plurality of second addresses and generate decoder control signals for application to the plurality of sub-decoder circuits; and
wherein each of the plurality of sub-decoder circuits generates one word line signal on a selected word line in response to said decoder control signals.

Assignees

• St Microelectronics Int Nv

Inventors

• Rawat Harsh
• Chawla Nitin
• Kumar Promod
• Dhori Kedar Janardan
• Ayodhyawasi Manuj

Classifications

• G11C7/1096

  Write circuits, e.g. I/O line write drivers · CPC title

• G11C7/109

  Control signal input circuits · CPC title

• G11C7/1087

  Data input latches · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C7/1057

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title