In-memory computation circuit using static random access memory (SRAM) array segmentation

Patent metadata

Field	Value
Publication number	US-12406705-B2
Application number	US-202318136491-A
Country	US
Kind code	B2
Filing date	Apr 19, 2023
Priority date	May 25, 2022
Publication date	Sep 2, 2025
Grant date	Sep 2, 2025

Abstract

An in-memory computation circuit includes a memory array including sub-arrays of with SRAM cells connected in rows by word lines and in columns by local bit lines. A row controller circuit selectively actuates one word line per sub-array for an in-memory compute operation. A global bit line is capacitively coupled to many local bit lines in either a column direction or row direction. An analog global output voltage on each global bit line is an average of local bit line voltages on the capacitively coupled local bit lines. The analog global output voltage is sampled and converted by an analog-to-digital converter (ADC) circuit to generate a digital decision signal output for the in-memory compute operation.

First claim

The invention claimed is:

1. An in-memory computation circuit, comprising:
a memory array including a plurality of sub-arrays, wherein each sub-array includes memory cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the memory cells of the row, and each column including a local bit line connected to the memory cells of the column, said memory cells configured to store bits of weight data for an in-memory compute operation;
a word line driver circuit for each row having an output connected to drive the word line of the row;
a row controller circuit configured to simultaneously actuate only one word line per sub-array for the in-memory compute operation by applying pulses through the word line driver circuits to the word lines; and
a plurality of global bit lines, where each global bit line is capacitively coupled to a plurality of local bit lines.

2. The circuit of claim 1 , wherein each global bit line extends parallel to corresponding columns of memory cells in the plurality of sub-arrays, and wherein each global bit line is capacitively coupled to the local bit lines of the corresponding columns of memory cells in the plurality of sub-arrays.

3. The circuit of claim 2 , wherein an analog global output voltage on each global bit line is an average of local bit line voltages on said local bit lines of the corresponding columns of memory cells in the plurality of sub-arrays.

4. The circuit of claim 3 , further comprising a computation circuit coupled to each global bit line and including an analog-to-digital converter (ADC) circuit configured to sample and convert the analog global output voltage from the global bit line to generate a digital decision output for the in-memory compute operation.

5. The circuit of claim 1 , wherein each global bit line extends parallel to rows of memory cells in a corresponding sub-array of the plurality of sub-arrays, and wherein each global bit line is capacitively coupled to the local bit lines for columns of memory cells in the corresponding sub-array of the plurality of sub-arrays.

6. The circuit of claim 5 , wherein an analog global output voltage on each global bit line is an average of local bit line voltages on said local bit lines for columns of memory cells in the corresponding sub-array of the plurality of sub-arrays.

7. The circuit of claim 6 , further comprising a computation circuit coupled to each global bit line and including an analog-to-digital converter (ADC) circuit configured to sample and convert the analog global output voltage from the global bit line to generate a digital decision output for the in-memory compute operation.

8. The circuit of claim 1 , wherein the pulses applied through the word line driver circuits to the word lines carry feature data for the in-memory compute operation.

9. The circuit of claim 1 , wherein the pulses have a pulse width sufficient to ensure full discharge of the local bit line dependent on a bit logic state of the weight data.

10. The circuit of claim 1 , further comprising a computation circuit coupled to each global bit line and including an analog-to-digital converter (ADC) circuit configured to sample and convert an analog global output voltage from the global bit line to generate a digital decision output for the in-memory compute operation.

11. The circuit of claim 1 , further comprising a switching circuit configured to selectively connect at least two global bit lines of the plurality of global bit lines for charge sharing to generate an analog global output voltage.

12. The circuit of claim 11 , further comprising a computation circuit including an analog-to-digital converter (ADC) circuit configured to sample and convert the analog global output voltage to generate a digital decision output for the in-memory compute operation.

13. The circuit of claim 1 , further comprising a coupling circuit between each local bit line and the global bit line, wherein each coupling circuit comprises a capacitor having a first terminal coupled to the local bit line and a second terminal coupled to the global bit line.

14. The circuit of claim 13 , wherein the capacitors of the coupling circuits coupled to a same global bit line of the plurality of global bit lines have a same capacitance.

15. The circuit of claim 13 , wherein the capacitors of the coupling circuits coupled to a same global bit line of the plurality of global bit lines have different capacitances, and wherein the different capacitances are weighted.

16. The circuit of claim 1 , further comprising a coupling circuit between each local bit line and the global bit line, wherein each coupling circuit comprises:
a first capacitor having a first terminal coupled to the local bit line and a second terminal coupled to the global bit line; and
a second capacitor having a first terminal coupled to the local bit line and a second terminal coupled to the global bit line.

17. The circuit of claim 16 , wherein the first capacitor and second capacitor in each coupling circuit have different capacitances, and wherein the different capacitances are weighted.

18. The circuit of claim 17 , where each coupling circuit further comprises:
a first switch coupled in series with the first capacitor between the local bit line and the global bit line; and
a second switch coupled in series with the first capacitor between the local bit line and the global bit line;
wherein the first and second switches are selectively actuated in response to bits of feature data for the in-memory compute operation.

19. The circuit of claim 1 , further comprising a coupling circuit between each local bit line and the global bit line, wherein each coupling circuit comprises:
a first logical combination circuit configured to logically combine a signal on the local bit line with a first bit of feature data for the in-memory compute operation;
a first capacitor having a first terminal coupled to an output of the first logical combination circuit and a second terminal coupled to the global bit line;
a second logical combination circuit configured to logically combine the signal on the local bit line with a second bit of the feature data; and
a second capacitor having a first terminal coupled to the local bit line and a second terminal coupled to the global bit line.

20. The circuit of claim 19 , wherein the first capacitor and second capacitor in each coupling circuit have different capacitances, and wherein the different capacitances are weighted.

21. The circuit of claim 20 , where each coupling circuit further comprises:
a first switch coupled in series with the first capacitor between the local bit line and the global bit line, wherein the first switch is selectively actuated in response to a first control signal; and
a second switch coupled in series with the first capacitor between the local bit line and the global bit line, wherein the second switch is selectively actuated in response to a second control signal.

22. The circuit of claim 21 , wherein the first and second control signals are dependent on said first and second bits of the feature data.

23. The circuit of claim 1 , further comprising:
a capacitor for each global bit line; and
a switch configured to selectively couple the global bit line to the capacitor, wherein said switch is actuated in response to a control signal.

24. The circuit of claim 23 , further comprising a computation circuit including

Assignees

• St Microelectronics Int Nv

Inventors

• Rawat Harsh
• Dhori Kedar Janardan
• Kumar Promod
• Chawla Nitin
• Ayodhyawasi Manuj

Classifications

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G06N3/065

  Analogue means · CPC title

• G11C7/16 Primary

  Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters · CPC title

• G11C7/1006 Primary

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title