Bit-cell architecture based in-memory compute

Patent metadata

Field	Value
Publication number	US-2025078883-A1
Application number	US-202418951392-A
Country	US
Kind code	A1
Filing date	Nov 18, 2024
Priority date	Sep 30, 2021
Publication date	Mar 6, 2025
Grant date	—

Abstract

A memory array includes a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns. The memory array also includes a plurality of in-memory-compute (IMC) cells arranged as a set of rows of IMC cells intersecting the plurality of columns of the memory array. Each of the IMC cells of the memory array includes a first bit-cell having a latch, a write-bit line and a complementary write-bit line, and a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell.

First claim

1 . A device, comprising:
an in-memory-compute (IMC) memory array including:
a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns of the IMC memory array; and
a plurality of in-memory-compute (IMC) cells of the IMC memory array arranged as a set of rows of IMC cells intersecting the plurality of columns of the IMC memory array, each of the IMC cells of the IMC memory array having:
a first bit-cell having a latch, a write-bit line and a complementary write- bit line; and
a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell; and

accumulation circuitry coupled to columns of the IMC memory array, wherein the IMC memory array comprises pre-charging circuitry coupled to the plurality of IMC cells.

2 . The device of claim 1 wherein the pre-charging circuitry comprises masking circuitry, which, in operation, selectively masks outputs of columns of the array.

3 . The device of claim 1 , wherein the accumulation circuitry comprises a plurality of adders.

4 . The device of claim 1 , wherein the accumulation circuitry comprises one or more capacitors.

5 . The device of claim 4 , comprising one or more bias capacitors selectively coupleable to the accumulation circuitry.

6 . The device of claim 4 , comprising readout circuitry coupled to the one or more capacitors.

7 . The device of claim 6 , wherein the readout circuitry comprises an analog-to-digital converter.

8 . The device of claim 6 , wherein the readout circuitry comprises a successive approximation circuit.

9 . The device of claim 1 , wherein the plurality of bit-cells, the first bit-cells of the IMC cells, and the second bit-cells of the IMC cells are foundry bit-cells.

10 . The device of claim 1 , wherein the first bit-cells of the IMC cells comprise a read-word line and a read-bit line, and the second bit-cells of the IMC cells comprise a read-word line and a read-bit line, and, in an in-memory-compute mode of operation, the IMC cells selectively XOR data stored in the latches with data provided on the read-word lines.

11 . The device of claim 10 , wherein in the in-memory-compute mode of operation, the IMC cells selectively XOR feature data stored in the latches with weight data provided on the read-word lines.

12 . A method, comprising:
storing data in an in-memory-compute (IMC) memory array, the IMC memory array including:
a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns of the IMC memory array; and
a plurality of IMC cells of the IMC memory array arranged as a set of rows of IMC cells intersecting the plurality of columns of the IMC memory array, each of the IMC cells of the IMC memory array having:
a first bit-cell having a latch, a write-bit line and a complementary write-bit line; and
a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell;

performing a multiplication operation on data stored in the IMC memory array, the performing the multiplication operation including:
precharging IMC cells of the plurality of IMC cells of the IMC memory array; and
accumulating results for columns of the plurality of IMC cells of the IMC memory array.

13 . The method of claim 12 , comprising controlling an operation mode of individual rows of the set of rows of IMC cells.

14 . The method of claim 12 , wherein the multiplying is performed for a set of the plurality of columns and the method comprises accumulating multiplication results for the set of columns.

15 . The method of claim 14 , comprising accumulating multiplication results of a plurality of IMC memory arrays.

16 . The method of claim 15 , comprising applying a bias to the accumulated multiplication results.

17 . The method of claim 12 , wherein the precharging comprises selectively masking outputs of columns of the array.

18 . A non-transitory computer-readable medium having contents which configure a processing device to perform a method, the method comprising:
storing data in an in-memory-compute (IMC) memory array, the IMC memory array including:
a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns of the IMC memory array; and
a plurality of IMC cells of the IMC memory array arranged as a set of rows of IMC cells intersecting the plurality of columns of the IMC memory array, each of the IMC cells of the IMC memory array having:
a first bit-cell having a latch, a write-bit line and a complementary write-bit line; and
a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell;

performing a multiplication operation on data stored in the IMC memory array, the performing the multiplication operation including:
precharging IMC cells of the plurality of IMC cells of the IMC memory array; and
accumulating results for columns of the plurality of IMC cells of the IMC memory array.

19 . The non-transitory computer-readable medium of claim 18 , wherein the first bit-cells of the IMC cells comprise a read-word line and a read-bit line, and the second bit-cells of the IMC cells comprise a read-word line and a read-bit line, and, the multiplying comprises selectively XORing data stored in the latches with data provided on the read-word lines.

20 . The non-transitory computer-readable medium of claim 18 , wherein the contents comprising instructions executable by the processing device.

Assignees

• St Microelectronics Int Nv

Inventors

• Rawat Harsh
• Dhori Kedar Janardan
• Kumar Promod
• Chawla Nitin
• Ayodhyawasi Manuj

Classifications

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C7/1069

  I/O lines read out arrangements · CPC title

• G11C11/412

  using field-effect transistors only · CPC title

• G11C11/54

  using elements simulating biological cells, e.g. neuron · CPC title

• G06N3/063

  using electronic means · CPC title