Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Patent metadata

Field	Value
Publication number	US-12237007-B2
Application number	US-202217852567-A
Country	US
Kind code	B2
Filing date	Jun 29, 2022
Priority date	Jul 9, 2021
Publication date	Feb 25, 2025
Grant date	Feb 25, 2025

Abstract

A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line clamping circuit includes a sensing circuit that compares the analog voltages on a given pair of bit lines to a threshold voltage. A voltage clamp circuit is actuated in response to the comparison to preclude the analog voltages on the given pair of bit lines from decreasing below a clamping voltage level.

First claim

What is claimed is:

1. A circuit, comprising:
a memory array including a plurality of static random access memory (SRAM) cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the SRAM cells of the row, and each column including at least one bit line connected to the SRAM cells of the column;
a word line driver circuit for each row having an output connected to drive the word line of the row;
a row controller circuit configured to simultaneously actuate the plurality of word lines by applying pulses through the word line driver circuits to the word lines for an in-memory compute operation;
a column processing circuit connected to the at least one bit line for each column and configured to process an analog voltage developed on the bit lines in response to the simultaneous actuation of the plurality of word lines to generate a decision output for the in-memory compute operation; and
a bit line clamping circuit comprising a sensing circuit configured to compare the analog voltage on a given bit line to a threshold voltage and a voltage clamp circuit that is actuated in response to the comparison to preclude the analog voltage on that given bit line from decreasing below a clamping voltage level.

2. The circuit of claim 1 , wherein the voltage clamp circuit comprises:
a transistor having a source-drain path coupled between a supply voltage node and the given bit line;
wherein a gate terminal of the transistor is configured to receive a clamp actuate signal that is asserted by the sensing circuit in response to the comparison.

3. The circuit of claim 1 , wherein the sensing circuit generates a clamp actuate signal, and further comprising a flag signal generated in response to the clamp actuate signal, wherein the flag signal is indicative of a loss of sensitivity of the decision output for the in-memory compute operation.

4. The circuit of claim 1 , wherein the voltage clamp circuit comprises:
a first transistor having a source-drain path coupled between a supply voltage node and the given bit line;
a second transistor having a source-drain path coupled in series with the source-drain path of the first transistor;
wherein a gate terminal of the first transistor is configured to receive a clamp actuate signal that is asserted by the sensing circuit in response to the comparison; and
wherein a gate terminal of the second transistor is configured to receive a control signal.

5. The circuit of claim 4 , further comprising a flag signal generated in response to the clamp actuate signal, wherein the flag signal is indicative of a loss of sensitivity of the decision output for the in-memory compute operation.

6. The circuit of claim 1 , wherein the sensing circuit comprises a Schmitt trigger circuit.

7. The circuit of claim 1 , wherein the bit line clamping circuit further comprises a logic circuit configured to logically combine an output of the sensing circuit with a clamping circuit enable signal, wherein said logic circuit is configured, when said clamping circuit enable signal is deasserted, to block actuation of the voltage clamp circuit.

8. The circuit of claim 1 , wherein said given bit line is one of a pair of bit lines for the SRAM cell.

9. The circuit of claim 1 , wherein the bit line clamping circuit is a component of a bit line precharge circuit.

10. A circuit, comprising:
a memory array including a plurality of static random access memory (SRAM) cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the SRAM cells of the row, and each column including at least one bit line connected to the SRAM cells of the column;
a word line driver circuit for each row having an output connected to drive the word line of the row;
a row controller circuit configured to simultaneously actuate the plurality of word lines by applying pulses through the word line driver circuits to the word lines for an in-memory compute operation;
a column processing circuit connected to the at least one bit line for each column and configured to process an analog voltage developed on the bit lines in response to the simultaneous actuation of the plurality of word lines to generate a decision output for the in-memory compute operation; and
a bit line clamping circuit comprising a sensing circuit configured to compare the analog voltage on a given bit line to a threshold voltage and a voltage clamp circuit that is actuated in response to the comparison to preclude the analog voltage on that given bit line from decreasing below a clamping voltage level;
wherein the voltage clamp circuit comprises:
a first transistor having a source-drain path coupled between a supply voltage node and the given bit line;
a second transistor having a source-drain path coupled in series with the source-drain path of the first transistor;
wherein a gate terminal of the first transistor is configured to receive a clamp actuate signal that is asserted by the sensing circuit in response to the comparison;
wherein a gate terminal of the second transistor is configured to receive a control signal; and
wherein the control signal is an analog bias voltage, and a voltage level of the analog bias voltage is configured to control a strength of the clamping circuit in clamping the bit line to the clamping voltage level.

11. The circuit of claim 10 , further comprising:
a voltage generating circuit configured to generate the analog bias voltage in response to a setting signal; and
a control circuit configured to generate the setting signal for application to the voltage generator circuit.

12. The circuit of claim 11 , wherein the setting signal is configured to cause modulation of the analog bias voltage away from a nominal level in response to an applicable integrated circuit process corner for transistor devices of the SRAM cells.

13. The circuit of claim 11 , wherein the applicable integrated circuit process corner is indicated by a programmed code stored in the control circuit, and wherein the control circuit includes a lookup table (LUT) correlating the programmed code to a value of the setting signal.

14. The circuit of claim 11 , wherein the control circuit further comprises a temperature sensor, and wherein the setting signal is configured to cause a temperature dependent tuning of the analog bias voltage in response to applicable integrated circuit process corner.

15. The circuit of claim 14 , wherein the control circuit includes a lookup table (LUT) correlating sensed integrated circuit temperature to a tuning level for the value of the setting signal.

16. The circuit of claim 11 , wherein the control circuit further comprises a temperature sensor, and wherein the setting signal is configured to cause modulation of the analog bias voltage away from a nominal level in response to an integrated circuit temperature sensed by the temperature sensor.

17. The circuit of claim 16 , wherein the control circuit includes a lookup table (LUT) correlating sensed integrated circuit temperature to a value of the setting signal.

18. A circuit, comprising:
a memory array including a plurality of static random access memory (SRAM) cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the SRAM cells of the row, and each column including at least one bit line connected to the SRAM cells of the column;
a word line driver circuit for each row having an output connected to drive the word line of the row;
a row controller circuit configured to simulta

Assignees

• St Microelectronics Int Nv

Inventors

• Dhori Kedar Janardan
• Rawat Harsh
• Kumar Promod
• Chawla Nitin
• Ayodhyawasi Manuj

Classifications

• G11C11/419

  Read-write [R-W] circuits · CPC title

• G11C11/412

  using field-effect transistors only · CPC title

• G11C7/067

  Single-ended amplifiers · CPC title

• G11C7/062

  Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title