Computing system power management device, system and method

Patent metadata

Field	Value
Publication number	US-12292780-B2
Application number	US-202318338950-A
Country	US
Kind code	B2
Filing date	Jun 21, 2023
Priority date	Dec 13, 2019
Publication date	May 6, 2025
Grant date	May 6, 2025

Abstract

Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.

First claim

The invention claimed is:

1. A system on chip (SoC) device, comprising:
one or more processing cores; and
a memory coupled to the one or more processing cores, the memory including:
a plurality of memory circuits organized into a first set of memory circuits and a second set of memory circuits;
a common voltage regulator having an output coupled to respective gate driver nodes of the plurality of memory circuits, wherein the common voltage regulator, in operation, regulates a voltage provided to the plurality of memory circuits; and
memory control circuitry coupled to the plurality of memory circuits and the common voltage regulator, wherein the memory control circuitry, in operation:
controls transitions of memory circuits of the first set of memory circuits of the plurality of memory circuits between an active state and a retention state; and
maintains the second set of memory circuits of the plurality of memory circuits in the retention state, wherein,

the memory control circuitry comprises a set of active memory signal switches coupled to respective memory circuits of the first set of memory circuits,
a bias node of the second set of memory circuits is coupled to a bias node of the common voltage regulator, and
a bias node of a memory circuit of the first set of memory circuits is coupled to the bias node of the common voltage regulator via a first switch, and, in operation, the first switch is closed in response to opening of the respective active memory signal switch for the memory circuit of the first set of memory circuits.

2. The SoC device of claim 1 , comprising delay circuitry coupled to the first switch, wherein, in operation, the delay circuitry delays the closing of the first switch in response to the opening of the respective active memory signal switch for the memory circuit of the first set of memory circuits.

3. The SoC device of claim 1 , wherein the common voltage regulator is a low dropout regulator (LDO).

4. The SoC device of claim 1 , wherein the second set of memory circuits comprises multiple memory circuits.

5. The SoC device of claim 1 , wherein the first set of memory circuits comprises multiple memory circuits.

6. The SoC device of claim 5 , wherein the second set of memory circuits comprises a single memory circuit.

7. The SoC device of claim 1 , wherein a size of a memory circuit of the first set of memory circuits is larger than a size of a memory circuit of the second set of memory circuits.

8. The SoC device of claim 1 , comprising:
a second memory coupled to the one or more processing cores.

9. The SoC device of claim 8 , wherein the second memory comprises:
a second plurality of memory circuits organized into a third set of memory circuits and a fourth set of memory circuits;
a second common voltage regulator having an output coupled to respective gate driver nodes of the second plurality of memory circuits, wherein the second common voltage regulator, in operation, regulates a voltage provided to the second plurality of memory circuits; and
second memory control circuitry coupled to the second plurality of memory circuits and the second common voltage regulator, wherein the second memory control circuitry, in operation:
controls transitions of the third set of memory circuits of the second plurality of memory circuits between the active state and the retention state; and
maintains the fourth set of memory circuits of the second plurality of memory circuits in the retention state.

10. The SoC device of claim 9 , wherein a memory circuit of the second plurality of memory circuits comprises a memory array.

11. The SoC device of claim 1 , wherein, the one or more processing cores, in operation, implement a neural network using the memory, the implementing the neural network including generating signals to cause the memory control circuitry to selectively transition memory circuits of the first set of memory circuits between the active state and the retention state.

12. A memory, comprising:
a plurality of memory circuits organized into a first set of memory circuits and a second set of memory circuits;
a common voltage regulator having an output coupled to respective gate driver nodes of the plurality of memory circuits, wherein the common voltage regulator, in operation, regulates a voltage provided to the plurality of memory circuits; and
memory control circuitry coupled to the plurality of memory circuits and the common voltage regulator, wherein the memory control circuitry, in operation:
controls transitions of the first set of memory circuits of the plurality of memory circuits between an active state and a retention state; and
maintains the second set of memory circuits of the plurality of memory circuits in the retention state, wherein,
the memory control circuitry comprises a set of active memory signal switches coupled to respective memory circuits of the first set of memory circuits,
a bias node of the second set of memory circuits is coupled to a bias node of the common voltage regulator, and
a bias node of a memory circuit of the first set of memory circuits is coupled to the bias node of the common voltage regulator via a first switch, and, in operation, the first switch is closed in response to opening of the respective active memory signal switch for the memory circuit of the first set of memory circuits.

13. The memory of claim 12 , comprising delay circuitry coupled to the first switch, wherein, in operation, the delay circuitry delays the closing of the first switch in response to the opening of the respective active memory signal switch for the memory circuit of the first set of memory circuits.

14. The memory of claim 12 , wherein the second set of second memory circuits comprises a single memory circuit having a size smaller than a size of a memory circuit of the first set of memory circuits.

Assignees

• St Microelectronics Srl
• St Microelectronics Int Nv

Inventors

• Chawla Nitin
• Grover Anuj
• Desoli Giuseppe
• Dhori Kedar Janardan
• Boesch Thomas
• Kumar Promod

Classifications

• G11C11/413

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction · CPC title

• G06F15/7821

  Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• G05F3/24

  wherein the transistors are of the field-effect type only (G05F3/205, G05F3/26, G05F3/30 take precedence) · CPC title

• G06N3/063

  using electronic means · CPC title