At-speed transition fault testing for a multi-port and multi-clock memory

Patent metadata

Field	Value
Publication number	US-12437825-B2
Application number	US-202318228118-A
Country	US
Kind code	B2
Filing date	Jul 31, 2023
Priority date	Sep 30, 2022
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A memory circuit includes an address port, a data input port and a data output port. An upstream shadow logic circuit is coupled to provide address data to the address port of the memory circuit and input data to the data input port of the memory circuit. A downstream shadow logic circuit is coupled to receive output data from the data output port of the memory circuit. The memory circuit includes a bypass path between the address port and the data output port. This bypass path is activated during a testing operation to pass bits of the address data (forming test data) applied by upstream shadow logic circuit from the address port to the data output port.

First claim

What is claimed is:

1. An integrated circuit system, comprising:
a memory circuit having: a memory array, a control circuit coupled to an address port, and input/output circuits coupled to a data input port and a data output port;
wherein the control circuit includes an address register configured to latch a read address in response to a read clock;
wherein each input/output circuit includes a first data path controlled by a write clock and coupling a data input of the data input port to a write bit line of the memory array and a second data path controlled by the read clock and coupling a read bit line of the memory array to a data output of the data output port;
wherein the second data path in each input/output circuit comprises a multiplexer circuit having a first input coupled to the read bit line, a second input coupled to a bypass path and an output coupled to the data output;
wherein a test bit is applied responsive to the read clock to the second input of the multiplexer in each input/output circuit; and
wherein the multiplexer is controlled to select the second input during a testing operation.

2. The integrated circuit system of claim 1 , wherein the memory array of the memory circuit comprises memory cells having separate read ports and write ports.

3. The integrated circuit system of claim 1 , wherein the second data path in each input/output circuit comprises a latch circuit configured to latch data from the read bit line of the memory array in response to the read clock.

4. The integrated circuit system of claim 1 , wherein the test bit is an address bit of the read address latched in the address register in response to the read clock.

5. The integrated circuit system of claim 3 , wherein said bypass path includes a delay circuit configured to delay application of the address bit of the read address to the second input of the multiplexer in each input/output circuit by a delay time.

6. The integrated circuit system of claim 5 , wherein the delay time is set so that timing of test signal propagation from the register through the bypass path and the second input of the multiplexer to the data output is equal to the timing of memory access for read from the memory array through the second data path.

7. The integrated circuit system of claim 4 , further comprising shadow logic upstream of the address port, wherein said shadow logic provides the read address during the testing operation.

8. The integrated circuit system of claim 7 , further comprising a scan register for the testing operation coupled to the shadow logic upstream of the data input port.

9. The integrated circuit system of claim 4 , further comprising a built-in self test (BIST) circuit configured to supply the read address during the testing operation.

10. The integrated circuit system of claim 9 , wherein the BIST circuit is further coupled to the data output port.

11. The integrated circuit system of claim 1 , further comprising shadow logic downstream of the data output port.

12. The integrated circuit system of claim 11 , further comprising a scan register for the testing operation coupled to the shadow logic downstream of the data output port.

13. The integrated circuit system of claim 1 , further comprising shadow logic upstream of the data input port.

14. The integrated circuit system of claim 13 , further comprising a scan register for the testing operation coupled to the shadow logic upstream of the data input port.

15. The integrated circuit system of claim 1 , wherein the read clock and the write clock are asynchronous.

16. The integrated circuit system of claim 1 , wherein the read clock and the write clock have different frequencies.

17. The integrated circuit system of claim 1 , wherein the memory array is divided into a plurality of sub-arrays, each sub-array including a local read bit line, and wherein each input/output circuit comprises read logic having inputs coupled to the local read bit lines from the plurality of sub-arrays and an output coupled to the second data path.

18. The integrated circuit system of claim 17 , wherein each input/output circuit further comprises a plurality of further data paths, each further data path coupling one of the plurality of local read bit lines to a corresponding one of a plurality of read data outputs of the data output port.

19. The integrated circuit system of claim 18 :
wherein the test bit is an address bit of the read address latched in the address register in response to the read clock;
wherein each further data path in each input/output circuit comprises a further multiplexer circuit having a first input coupled to the local read bit line, a second input coupled to the bypass path and an output coupled to the read data output;
wherein the address bit of the read address latched in the address register is applied to the second input of the further multiplexers in each input/output circuit; and
wherein the further multiplexers are controlled to select the second input during the testing operation.

20. The integrated circuit system of claim 19 , wherein the second data path in each input/output circuit comprises a latch circuit configured to latch data from the read bit line of the memory array in response to the read clock.

21. The integrated circuit system of claim 19 , wherein said bypass path includes a delay circuit configured to delay application of the address bit of the read address to the second input of the further multiplexers in each input/output circuit by a delay time.

22. The integrated circuit system of claim 21 , wherein the delay time is set so that timing of test signal propagation from the register through the bypass path and the second input of the further multiplexers to the read data outputs is equal to the timing of memory access for read from the memory array through the second data path.

23. The integrated circuit system of claim 19 , further comprising shadow logic downstream of the data output port.

24. The integrated circuit system of claim 23 , further comprising a scan register for the testing operation coupled to the shadow logic downstream of the data output port.

25. The integrated circuit system of claim 19 , further comprising shadow logic upstream of the data input port.

26. The integrated circuit system of claim 25 , further comprising a scan register for the testing operation coupled to the shadow logic upstream of the data input port.

27. The integrated circuit system of claim 19 , further comprising shadow logic upstream of the address port, wherein said shadow logic provides the read address during the testing operation.

28. The integrated circuit system of claim 27 , further comprising a scan register for the testing operation coupled to the shadow logic upstream of the data input port.

29. The integrated circuit system of claim 19 , further comprising a built-in self test (BIST) circuit configured to supply the read address during the testing operation.

30. The integrated circuit system of claim 29 , wherein the BIST circuit is further coupled to the data output port.

31. The integrated circuit system of claim 19 , wherein the read clock and the write clock are asynchronous.

32. An integrated circuit system, comprising:
a memory circuit an address port, a data input port and a data output port;

Assignees

• St Microelectronics Int Nv

Inventors

• Kumar Tanuj
• Chawla Hitesh
• Singh Bhupender
• Rawat Harsh
• Dhori Kedar Janardan
• Ayodhyawasi Manuj
• Chawla Nitin
• Kumar Promod

Classifications

• G11C29/12015

  comprising clock generation or timing circuitry · CPC title

• G11C29/32

  Serial access; Scan testing · CPC title

• G11C2029/1204

  Bit line control · CPC title

• G11C29/48

  Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths · CPC title

• G11C29/1201 Primary

  comprising I/O circuitry · CPC title